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Searched refs:pwr_p (Results 1 – 7 of 7) sorted by relevance

/titanic_50/usr/src/uts/sun4u/io/pci/
H A Dpci_pwr.c41 static void pci_pwr_update_comp(pci_pwr_t *pwr_p, pci_pwr_chld_t *p, int comp,
55 pci_pwr_get_info(pci_pwr_t *pwr_p, dev_info_t *dip) in pci_pwr_get_info() argument
59 ASSERT(PM_CAPABLE(pwr_p)); in pci_pwr_get_info()
60 ASSERT(MUTEX_HELD(&pwr_p->pwr_mutex)); in pci_pwr_get_info()
62 for (p = pwr_p->pwr_info; p != NULL; p = p->next) { in pci_pwr_get_info()
80 pci_pwr_create_info(pci_pwr_t *pwr_p, dev_info_t *dip) in pci_pwr_create_info() argument
84 ASSERT(PM_CAPABLE(pwr_p)); in pci_pwr_create_info()
92 mutex_enter(&pwr_p->pwr_mutex); in pci_pwr_create_info()
100 pwr_p->pwr_fp++; in pci_pwr_create_info()
102 p->next = pwr_p->pwr_info; in pci_pwr_create_info()
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H A Dpci_pci.c1231 pci_pwr_current_lvl(pci_pwr_t *pwr_p) in pci_pwr_current_lvl() argument
1240 ddi_get_instance(pwr_p->pwr_dip)); in pci_pwr_current_lvl()
/titanic_50/usr/src/uts/common/io/pciex/
H A Dpcie_pwr.c83 static int pcie_pwr_change(dev_info_t *dip, pcie_pwr_t *pwr_p, int new);
85 static int pwr_level_allowed(pcie_pwr_t *pwr_p);
87 pcie_pwr_t *pwr_p);
89 pcie_pwr_t *pwr_p);
90 static void pcie_pm_subrelease(dev_info_t *dip, pcie_pwr_t *pwr_p);
109 pcie_pwr_t *pwr_p = PCIE_NEXUS_PMINFO(dip); in pcie_power() local
110 int *counters = pwr_p->pwr_counters; in pcie_power()
111 int pmcaps = pwr_p->pwr_pmcaps; in pcie_power()
125 mutex_enter(&pwr_p->pwr_lock); in pcie_power()
127 ddi_driver_name(dip), ddi_get_instance(dip), pwr_p->pwr_func_lvl, in pcie_power()
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H A Dpcieb.c136 static int pcieb_pwr_init_and_raise(dev_info_t *dip, pcie_pwr_t *pwr_p);
1542 pcie_pwr_t *pwr_p; in pcieb_pwr_setup() local
1551 pwr_p = PCIE_NEXUS_PMINFO(dip); in pcieb_pwr_setup()
1552 ASSERT(pwr_p); in pcieb_pwr_setup()
1555 if (pci_config_setup(dip, &pwr_p->pwr_conf_hdl) != DDI_SUCCESS) { in pcieb_pwr_setup()
1560 conf_hdl = pwr_p->pwr_conf_hdl; in pcieb_pwr_setup()
1575 pwr_p->pwr_pmcsr_offset = cap_ptr + PCI_PMCSR; in pcieb_pwr_setup()
1579 pwr_p->pwr_pmcaps |= PCIE_SUPPORTS_D1; in pcieb_pwr_setup()
1583 pwr_p->pwr_pmcaps |= PCIE_SUPPORTS_D2; in pcieb_pwr_setup()
1589 if (pwr_p->pwr_pmcaps & PCIE_SUPPORTS_D2) in pcieb_pwr_setup()
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/titanic_50/usr/src/uts/sun4u/sys/pci/
H A Dpci_pwr.h134 #define PM_CAPABLE(pwr_p) (pwr_p != NULL) argument
135 #define SLOW_CAPABLE(pwr_p) ((pwr_p->pwr_flags &\ argument
144 extern void pci_pwr_component_busy(pci_pwr_t *pwr_p);
145 extern void pci_pwr_component_idle(pci_pwr_t *pwr_p);
146 extern int pci_pwr_current_lvl(pci_pwr_t *pwr_p);
147 extern int pci_pwr_new_lvl(pci_pwr_t *pwr_p);
148 extern int pci_pwr_ops(pci_pwr_t *pwr_p, dev_info_t *dip, void *impl_arg,
150 extern pci_pwr_chld_t *pci_pwr_get_info(pci_pwr_t *pwr_p, dev_info_t *);
151 extern void pci_pwr_create_info(pci_pwr_t *pwr_p, dev_info_t *);
152 extern void pci_pwr_rm_info(pci_pwr_t *pwr_p, dev_info_t *);
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/titanic_50/usr/src/uts/sun4u/io/px/
H A Dpx_lib4u.c1872 pcie_pwr_t *pwr_p; in px_goto_l23ready() local
1881 !(pwr_p = PCIE_NEXUS_PMINFO(px_p->px_dip))) in px_goto_l23ready()
1884 mutex_enter(&pwr_p->pwr_lock); in px_goto_l23ready()
1965 pwr_p->pwr_link_lvl = PM_LEVEL_L3; in px_goto_l23ready()
1968 mutex_exit(&pwr_p->pwr_lock); in px_goto_l23ready()
2001 pcie_pwr_t *pwr_p; in px_pre_pwron_check() local
2005 !(pwr_p = PCIE_NEXUS_PMINFO(px_p->px_dip))) in px_pre_pwron_check()
2013 return (pwr_p->pwr_link_lvl == PM_LEVEL_L3 ? DDI_SUCCESS : DDI_FAILURE); in px_pre_pwron_check()
2019 pcie_pwr_t *pwr_p; in px_goto_l0() local
2027 !(pwr_p = PCIE_NEXUS_PMINFO(px_p->px_dip))) in px_goto_l0()
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/titanic_50/usr/src/uts/sun4/io/px/
H A Dpx.c612 pcie_pwr_t *pwr_p; in px_pwr_setup() local
618 pwr_p = PCIE_NEXUS_PMINFO(dip); in px_pwr_setup()
619 ASSERT(pwr_p); in px_pwr_setup()
634 pwr_p->pwr_func_lvl = PM_LEVEL_D0; in px_pwr_setup()