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Searched refs:pstate (Results 1 – 25 of 107) sorted by relevance

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/titanic_50/usr/src/uts/sun4/ml/
H A Dsubr_asm.s136 rdpr %pstate, %o4
138 wrpr %o5, 0, %pstate
141 wrpr %g0, %o4, %pstate ! restore earlier pstate register value
153 rdpr %pstate, %o4
155 wrpr %o5, 0, %pstate ! clear IE, AM bits
158 wrpr %g0, %o4, %pstate ! restore earlier pstate register value
168 rdpr %pstate, %o4
170 wrpr %o5, 0, %pstate
173 wrpr %g0, %o4, %pstate ! restore earlier pstate register value
182 rdpr %pstate, %o4
[all …]
/titanic_50/usr/src/uts/sun4u/serengeti/ml/
H A Dsbdp.il.cpp75 rdpr %pstate, %o4
77 wrpr %g0, %g3, %pstate
99 wrpr %g0, %o4, %pstate ! restore earlier pstate register value
114 rdpr %pstate, %o3
116 wrpr %g0, %o4, %pstate ! clear AM to access 64 bit physaddr
130 wrpr %g0, %o3, %pstate ! restore earlier pstate
158 rdpr %pstate, %o2 /* read PSTATE reg */
160 wrpr %g0, %o3, %pstate
163 wrpr %g0, %o2, %pstate /* restore the PSTATE */
172 rdpr %pstate, %o2 /* read PSTATE reg */
[all …]
H A Dserengeti_asm.s75 rdpr %pstate, %o4
77 wrpr %o5, 0, %pstate ! clear IE, AM bits
80 wrpr %g0, %o4, %pstate ! restore earlier pstate register value
88 rdpr %pstate, %o4
90 wrpr %o5, 0, %pstate ! clear IE, AM bits
93 wrpr %g0, %o4, %pstate ! restore earlier pstate register value
H A Dsbdp_asm.s165 rdpr %pstate, %o3
167 wrpr %g0, %o4, %pstate
174 wrpr %g0, %o3, %pstate
316 rdpr %pstate, %o4
318 wrpr %o5, 0, %pstate ! clear IE, AM bits
322 wrpr %g0, %o4, %pstate ! restore earlier pstate register value
/titanic_50/usr/src/uts/sun4u/starfire/ml/
H A Ddrmach.il.cpp72 rdpr %pstate, %o4
74 wrpr %g0, %g3, %pstate
93 wrpr %g0, %o4, %pstate ! restore earlier pstate register value
110 rdpr %pstate, %o3
112 wrpr %g0, %o4, %pstate ! clear AM to access 64 bit physaddr
123 wrpr %g0, %o3, %pstate ! restore earlier pstate
143 rdpr %pstate, %o2 /* read PSTATE reg */
145 wrpr %g0, %o3, %pstate
148 wrpr %g0, %o2, %pstate /* restore the PSTATE */
157 rdpr %pstate, %o2 /* read PSTATE reg */
[all …]
/titanic_50/usr/src/uts/sun4u/lw8/ml/
H A Dlw8_platmod_asm.s75 rdpr %pstate, %o4
77 wrpr %o5, 0, %pstate ! clear IE, AM bits
80 wrpr %g0, %o4, %pstate ! restore earlier pstate register value
88 rdpr %pstate, %o4
90 wrpr %o5, 0, %pstate ! clear IE, AM bits
93 wrpr %g0, %o4, %pstate ! restore earlier pstate register value
/titanic_50/usr/src/uts/sun4u/daktari/ml/
H A Ddaktari_asm.s80 rdpr %pstate, %o4
82 wrpr %o5, 0, %pstate ! clear IE, AM bits
91 wrpr %g0, %o4, %pstate ! restore earlier pstate register value
104 rdpr %pstate, %o4
106 wrpr %o5, 0, %pstate ! clear IE, AM bits
115 wrpr %g0, %o4, %pstate ! restore earlier pstate register value
/titanic_50/usr/src/uts/sun4u/cherrystone/ml/
H A Dcherrystone_asm.s86 rdpr %pstate, %o4
88 wrpr %o5, 0, %pstate ! clear IE, AM bits
97 wrpr %g0, %o4, %pstate ! restore earlier pstate register value
110 rdpr %pstate, %o4
112 wrpr %o5, 0, %pstate ! clear IE, AM bits
121 wrpr %g0, %o4, %pstate ! restore earlier pstate register value
/titanic_50/usr/src/uts/sun4v/os/
H A Dmach_trap.c157 ptl1_showtrap(ptl1_state_t *pstate) in ptl1_showtrap() argument
159 ptl1_regs_t *rp = &pstate->ptl1_regs; in ptl1_showtrap()
169 uint32_t gl, ccr, asi, cwp, pstate; in ptl1_showtrap() local
172 pstate = (tstate >> TSTATE_PSTATE_SHIFT) & TSTATE_PSTATE_MASK; in ptl1_showtrap()
181 "%%pstate: %b\n", gl, ccr, asi, cwp, pstate, PSTATE_BITS); in ptl1_showtrap()
249 ptl1_state_t *pstate = &CPU->cpu_m.ptl1_state; in panic_showtrap() local
254 if (pstate->ptl1_entry_count) { in panic_showtrap()
255 ptl1_showtrap(pstate); in panic_showtrap()
264 ptl1_savetrap(panic_data_t *pdp, ptl1_state_t *pstate) in ptl1_savetrap() argument
266 ptl1_regs_t *rp = &pstate->ptl1_regs; in ptl1_savetrap()
[all …]
/titanic_50/usr/src/uts/sun4u/os/
H A Dmach_trap.c184 ptl1_showtrap(ptl1_state_t *pstate) in ptl1_showtrap() argument
186 ptl1_regs_t *rp = &pstate->ptl1_regs; in ptl1_showtrap()
195 uint32_t ccr, asi, cwp, pstate; in ptl1_showtrap() local
198 pstate = (tstate >> TSTATE_PSTATE_SHIFT) & TSTATE_PSTATE_MASK; in ptl1_showtrap()
206 "%%pstate: %b\n", ccr, asi, cwp, pstate, PSTATE_BITS); in ptl1_showtrap()
263 ptl1_state_t *pstate = &CPU->cpu_m.ptl1_state; in panic_showtrap() local
268 if (pstate->ptl1_entry_count) { in panic_showtrap()
269 ptl1_showtrap(pstate); in panic_showtrap()
278 ptl1_savetrap(panic_data_t *pdp, ptl1_state_t *pstate) in ptl1_savetrap() argument
280 ptl1_regs_t *rp = &pstate->ptl1_regs; in ptl1_savetrap()
[all …]
H A Dmach_cpu_states.c401 ptl1_state_t *pstate = &cpu->cpu_m.ptl1_state; in ptl1_init_cpu() local
409 pstate->ptl1_stktop = (uintptr_t)cpu + CPU_ALLOC_SIZE; in ptl1_init_cpu()
414 ptl1_panic_handler(ptl1_state_t *pstate) in ptl1_panic_handler() argument
449 uint_t reason = pstate->ptl1_regs.ptl1_g1; in ptl1_panic_handler()
450 uint_t tl = pstate->ptl1_regs.ptl1_trap_regs[0].ptl1_tl; in ptl1_panic_handler()
/titanic_50/usr/src/uts/sun4u/starcat/ml/
H A Dstarcat_asm.s69 rdpr %pstate, %o4
71 wrpr %o5, 0, %pstate ! clear IE, AM bits
74 wrpr %g0, %o4, %pstate ! restore pstate value
/titanic_50/usr/src/cmd/sgs/yacc/common/
H A Dy1.c78 ITEM **pstate; /* ptr to descriptions of the states */ variable
211 pstate = (ITEM **)malloc(sizeof (ITEM *)*(nstatesz+2)); in mktbls()
219 (pfirst == NULL) || (pempty == NULL) || (pstate == NULL) || in mktbls()
749 p1 = pstate[nstate]; in state()
750 p2 = pstate[nstate+1]; in state()
772 q1 = pstate[i]; in state()
773 q2 = pstate[i+1]; in state()
786 pstate[nstate+1] = pstate[nstate]; /* delete last state */ in state()
812 pstate[nstate+2] = p2; in state()
838 j = pstate[nstate+1];
[all …]
/titanic_50/usr/src/cmd/mdb/sparc/v9/kmdb/
H A Dclient_handler.s51 rdpr %pstate, %l4 ! Get the present pstate value
53 wrpr %l6, 0, %pstate ! Set PSTATE_AM = 0
56 wrpr %l4, 0, %pstate ! Just restore
/titanic_50/usr/src/uts/sun4u/io/
H A Dpanther_asm.s181 wrpr %g0, %o2, %pstate !restore pstate
274 rdpr %pstate, %o2
276 wrpr %g0, %g1, %pstate ! disable interrupts
342 rdpr %pstate, %o2
344 wrpr %g0, %g1, %pstate ! disable interrupts
379 wrpr %g0, %o2, %pstate !restore pstate
436 wrpr %g0, %o2, %pstate !restore pstate
525 rdpr %pstate, %o2
527 wrpr %g0, %g1, %pstate ! disable interrupts
591 rdpr %pstate, %o2
[all …]
/titanic_50/usr/src/lib/libdtrace_jni/java/src/org/opensolaris/os/dtrace/
H A DProcessState.java74 ProcessState pstate = (ProcessState)oldInstance;
76 "new", new Object[] { pstate.getProcessID(),
77 pstate.getState().name(),
78 pstate.getTerminationSignal(),
79 pstate.getTerminationSignalName(),
80 pstate.getExitStatus(),
81 pstate.getMessage() });
/titanic_50/usr/src/uts/sun4u/opl/ml/
H A Ddrmach.il.cpp75 rdpr %pstate, %g0
108 rdpr %pstate, %o3
110 wrpr %g0, %o4, %pstate
115 wrpr %g0, %o3, %pstate ! restore earlier pstate
/titanic_50/usr/src/cmd/mdb/sparc/kmdb/
H A Dkmdb_asmutil.s80 rdpr %pstate, %o0
83 wrpr %o0, %pstate
96 rdpr %pstate, %o0
99 wrpr %o0, %pstate
/titanic_50/usr/src/uts/sun4u/sys/
H A Dmachthread.h69 rdpr %pstate, scr; \
71 wrpr r, 0, %pstate; \
76 wrpr scr, 0, %pstate
254 rdpr %pstate, scr1; \
255 wrpr scr1, PSTATE_AG, %pstate; \
262 rdpr %pstate, %g5; \
263 wrpr %g5, PSTATE_AG, %pstate; \
/titanic_50/usr/src/uts/i86pc/sys/
H A Dcpu_acpi.h50 #define CPU_ACPI_FREQ(pstate) pstate->ps_freq argument
51 #define CPU_ACPI_PSTATE_TRANSLAT(pstate) pstate->ps_translat argument
52 #define CPU_ACPI_PSTATE_CTRL(pstate) pstate->ps_ctrl argument
/titanic_50/usr/src/uts/sun4u/ml/
H A Dmach_locore.s240 wrpr %g0, PSTATE_KERN, %pstate
840 rdpr %pstate, %l1
841 wrpr %l1, PSTATE_IE, %pstate
844 wrpr %l1, PSTATE_IE | PSTATE_AG, %pstate
958 rdpr %pstate, %o2
968 wrpr %o2, PSTATE_IE, %pstate /* disable interrupts */
980 wrpr %g0, %o2, %pstate /* enable interrupt */
1617 rdpr %pstate, %l4 ! disable interrupts
1619 wrpr %g0, %o2, %pstate
1628 wrpr %g0, %l4, %pstate ! restore interrupt state
[all …]
/titanic_50/usr/src/uts/sun4u/cpu/
H A Dspitfire_asm.s216 rdpr %pstate, tmp1 ;\
218 wrpr tmp2, 0, %pstate ;\
236 wrpr %g0, tmp1, %pstate
453 rdpr %pstate, %o5
461 wrpr %o4, 0, %pstate
507 wrpr %g0, %o5, %pstate /* enable interrupts */
820 rdpr %pstate, %g4 ! current pstate (restored later)
822 wrpr %g0, %g5, %pstate ! disable interrupts
848 wrpr %g0, %g4, %pstate ! restore earlier pstate
902 rdpr %pstate, %i5
[all …]
H A Dus3_common_asm.s194 rdpr %pstate, %o5
202 wrpr %o4, 0, %pstate
221 wrpr %g0, %o5, %pstate /* enable interrupts */
252 wrpr %g0, %o5, %pstate /* enable interrupts */
884 rdpr %pstate, %o5
886 wrpr %g0, %o3, %pstate
951 wrpr %g0, %o5, %pstate
975 rdpr %pstate, %o5
977 wrpr %g0, %o3, %pstate
1004 wrpr %g0, %o5, %pstate
[all …]
/titanic_50/usr/src/cmd/mdb/sun4u/v9/kmdb/
H A Dmach_asmutil.h49 wrpr %g0, PTSTATE_KERN_COMMON, %pstate /* AG = 0 */
52 wrpr %o4, %pstate /* use TL1 globals, set %pstate from %o4 */;\
67 wrpr reg1, %pstate
/titanic_50/usr/src/lib/libtnfctl/
H A Dprb_rtld.c244 prb_proc_state_t pstate; in prb_rtld_wait() local
282 prbstat = prb_proc_state(proc_p, &pstate); in prb_rtld_wait()
289 if (pstate.ps_issysentry && (pstate.ps_syscallnum == SYS_exit)) { in prb_rtld_wait()
294 if (!(pstate.ps_issysexit && (pstate.ps_syscallnum == SYS_getpid))) { in prb_rtld_wait()

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