| /titanic_50/usr/src/uts/sparc/fpu/ |
| H A D | iu_simulator.c | 44 struct regs *pregs, /* Pointer to PCB image of registers. */ in fbcc_sim() argument
141 tpc = pregs->r_pc; in fbcc_sim()
144 pregs->r_pc = tpc + in fbcc_sim()
147 pregs->r_pc = tpc + in fbcc_sim()
150 pregs->r_npc = pregs->r_pc + 4; in fbcc_sim()
152 pregs->r_pc = pregs->r_npc; in fbcc_sim()
154 pregs->r_npc = tpc + in fbcc_sim()
157 pregs->r_npc = tpc + in fbcc_sim()
163 pregs->r_pc = pregs->r_npc + 4; in fbcc_sim()
164 pregs->r_npc += 8; in fbcc_sim()
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| H A D | fpu_simulator.c | 538 struct regs *pregs, /* Pointer to PCB image of registers. */ in fpu_vis_sim() argument
572 pregs, (ulong_t *)pregs->r_sp, pfp); in fpu_vis_sim()
579 pregs->r_pc = pregs->r_npc; in fpu_vis_sim()
580 pregs->r_npc += 4; in fpu_vis_sim()
584 ftt = _fp_iu_simulator(pfpsd, fp.inst, pregs, in fpu_vis_sim()
585 (ulong_t *)pregs->r_sp, pfp); in fpu_vis_sim()
626 struct regs *pregs, /* Pointer to PCB image of registers. */ in fp_emulator() argument
658 pregs->r_pc = pregs->r_npc; in fp_emulator()
659 pregs->r_npc += 4; in fp_emulator()
672 pregs, prw, pfp); in fp_emulator()
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| /titanic_50/usr/src/uts/sparc/v9/fpu/ |
| H A D | v9instr.c | 51 struct regs *pregs, /* Pointer to PCB image of registers. */ in fldst() argument
67 asi = (uint32_t)((pregs->r_tstate >> TSTATE_ASI_SHIFT) & in fldst()
74 return (vis_fldst(pfpsd, pinst, pregs, prw, asi)); in fldst()
78 ftt = read_iureg(pfpsd, pinst.rs1, pregs, prw, &fea); in fldst()
81 ftt = read_iureg(pfpsd, pinst.rs2, pregs, prw, &tea); in fldst()
88 ftt = read_iureg(pfpsd, pinst.rs1, pregs, prw, &tea); in fldst()
132 switch (do_unaligned(pregs, &badaddr)) { in fldst()
140 pregs->r_pc = pregs->r_npc; /* Do not retry emulated instruction. */ in fldst()
141 pregs->r_npc += 4; in fldst()
276 struct regs *pregs; in fmovcc_icc() local
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| H A D | uword.c | 195 struct regs *pregs, /* Pointer to PCB image of registers. */ in read_iureg() argument
207 preg = &pregs->r_ps; /* globals and outs */ in read_iureg()
210 } else if (USERMODE(pregs->r_tstate)) { /* locals and ins */ in read_iureg()
257 struct regs *pregs, /* Pointer to PCB image of registers. */ in write_iureg() argument
267 preg = &pregs->r_ps; /* globals and outs */ in write_iureg()
270 } else if (USERMODE(pregs->r_tstate)) { /* locals and ins */ in write_iureg()
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| /titanic_50/usr/src/uts/sun4/os/ |
| H A D | visinstr.c | 82 struct regs *pregs, /* Pointer to PCB image of registers. */ in vis_fpu_simulator() argument
95 ASSERT(USERMODE(pregs->r_tstate)); in vis_fpu_simulator()
123 ftt = vis_edge(pfpsd, f.inst, pregs, prw); in vis_fpu_simulator()
128 ftt = vis_array(pfpsd, f.inst, pregs, prw); in vis_fpu_simulator()
132 ftt = vis_alignaddr(pfpsd, f.inst, pregs, prw, fp); in vis_fpu_simulator()
135 ftt = vis_bmask(pfpsd, f.inst, pregs, prw, fp); in vis_fpu_simulator()
145 ftt = vis_fcmp(pfpsd, f.inst, pregs, prw); in vis_fpu_simulator()
165 ftt = vis_pdist(pfpsd, pinst, pregs, prw, f.inst.opf); in vis_fpu_simulator()
362 pregs->r_pc = pregs->r_npc; /* Do not retry emulated instruction. */ in vis_fpu_simulator()
363 pregs->r_npc += 4; in vis_fpu_simulator()
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| /titanic_50/usr/src/cmd/mdb/sparc/mdb/ |
| H A D | proc_isadep.c | 598 const prgreg_t *pregs = &gregs->gregs[0]; in pt_frameregs() local
603 mdb_printf("%<b>%0?lr %s%</b>(", pregs[R_SP], "?"); in pt_frameregs()
605 mdb_printf("%<b>%0?lr %a%</b>(", pregs[R_SP], pc); in pt_frameregs()
618 pregs[R_L0], pregs[R_L1], pregs[R_L2], pregs[R_L3]); in pt_frameregs()
621 pregs[R_L4], pregs[R_L5], pregs[R_L6], pregs[R_L7]); in pt_frameregs()
623 if (pregs[R_FP] != 0 && (pregs[R_FP] + STACK_BIAS) != 0) in pt_frameregs()
625 buf, sizeof (buf), pregs[R_I7]) != pregs[R_I7]) in pt_frameregs()
626 mdb_printf("%-#25a%s\n", pregs[R_I7], buf); in pt_frameregs()
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| /titanic_50/usr/src/uts/sparc/sys/fpu/ |
| H A D | fpu_simulator.h | 396 struct regs *pregs, fsr_type *pfsr, uint64_t gsr, uint32_t inst);
456 struct regs *pregs, /* Pointer to PCB image of registers. */
|