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Searched refs:pci_size_hi (Results 1 – 25 of 33) sorted by relevance

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/titanic_50/usr/src/uts/sun4/io/px/
H A Dpx_util.c153 rp->pci_size_hi, rp->pci_size_low); in px_reloc_reg()
203 rp->pci_size_hi, rp->pci_size_low, i); in px_reloc_reg()
222 reg_sz = (uint64_t)px_rp->pci_size_hi << 32 | px_rp->pci_size_low; in px_xlate_reg()
570 ((uint64_t)pci_rp[rnumber].pci_size_hi << 32); in px_get_reg_set_size()
H A Dpx_tools.c480 dev_regspec.pci_size_hi = 0; /* Not used. */ in pxtool_get_phys_addr()
/titanic_50/usr/src/uts/sun4u/opl/io/pcicmu/
H A Dpcmu_util.c151 rp->pci_size_hi, rp->pci_size_low); in pcmu_reloc_reg()
158 if (rp->pci_phys_mid != 0 || rp->pci_size_hi != 0) { in pcmu_reloc_reg()
180 rp->pci_size_hi, rp->pci_size_low); in pcmu_reloc_reg()
452 ((uint64_t)pcmu_rp[rnumber].pci_size_hi << 32); in pcmu_get_reg_set_size()
/titanic_50/usr/src/uts/common/io/
H A Dbusra.c1052 ((uint64_t)(regs[i].pci_size_hi) << 32) | in pci_resource_setup()
1361 range_len = ((uint64_t)(regs[i].pci_size_hi) << 32) | in pci_get_available_prop()
1391 newregs[j].pci_size_hi = (uint32_t)(dlen >> 32); in pci_get_available_prop()
1403 newregs[j].pci_size_hi = (uint32_t)(dlen >> 32); in pci_get_available_prop()
1523 range_len = ((uint64_t)(regs[i].pci_size_hi) << 32) | in pci_put_available_prop()
1604 newregs[j].pci_size_hi = (uint32_t)(len >> 32); in pci_put_available_prop()
1618 newregs[k].pci_size_hi = (uint32_t)(len >> 32); in pci_put_available_prop()
1643 newregs[j].pci_size_hi = (uint32_t)(len >> 32); in pci_put_available_prop()
1672 newregs[0].pci_size_hi = (uint32_t)(len >> 32); in pci_put_available_prop()
/titanic_50/usr/src/uts/sun4u/io/pci/
H A Dpci_util.c165 rp->pci_size_hi, rp->pci_size_low); in pci_reloc_reg()
171 if (rp->pci_phys_mid != 0 || rp->pci_size_hi != 0) { in pci_reloc_reg()
203 rp->pci_size_hi, rp->pci_size_low); in pci_reloc_reg()
H A Dsimba.c639 ((uint64_t)drv_regp[rn].pci_size_hi << 32); in simba_ctlops()
H A Dpci.c1182 ((uint64_t)pci_rp[rnumber].pci_size_hi << 32); in get_reg_set_size()
/titanic_50/usr/src/uts/sparc/io/pciex/
H A Dpcieb_sparc.c412 reg_spec[rnum].pci_size_hi = addr_spec[anum].pci_size_hi; in plx_ro_disable()
/titanic_50/usr/src/uts/i86pc/io/pci/
H A Dpci.c441 reg.regspec_size = (uint64_t)pci_rp->pci_size_hi << 32 | in pci_bus_map()
491 (uint64_t)pci_rp->pci_size_hi << 32; in pci_bus_map()
589 (uint64_t)drv_regp[rn].pci_size_hi << 32; in pci_ctlops()
/titanic_50/usr/src/uts/intel/io/intel_nhm/
H A Dnhm_pci_cfg.c50 reg.pci_size_hi = 0; in nhm_pci_cfg_setup()
/titanic_50/usr/src/uts/i86pc/io/pciex/
H A Dnpe.c531 reg.regspec_size = (uint64_t)pci_rp->pci_size_hi << 32 | in npe_bus_map()
630 (uint64_t)pci_rp->pci_size_hi << 32; in npe_bus_map()
757 (uint64_t)drv_regp[rn].pci_size_hi << 32; in npe_ctlops()
/titanic_50/usr/src/uts/intel/io/intel_nb5000/
H A Dnb_pci_cfg.c55 reg.pci_size_hi = 0; in nb_pci_cfg_setup()
/titanic_50/usr/src/uts/sun4/io/efcode/
H A Dfcpci.c560 p.pci_size_hi = 0; in pfc_map_in()
852 p.pci_size_hi = p.pci_size_low = 0; in pfc_config_fetch()
984 p.pci_size_hi = p.pci_size_low = 0; in pfc_config_store()
1351 config.pci_size_hi = config.pci_size_low = 0; in pci_alloc_resource()
1578 config.pci_size_hi = config.pci_size_low = 0; in pci_free_resource()
/titanic_50/usr/src/uts/sun4/io/
H A Dpcicfg.c1982 (reg[i].pci_size_hi != 0)) { in pcicfg_bridge_assign()
2127 (reg[i].pci_size_hi != 0)) { in pcicfg_device_assign()
2295 (assigned[i].pci_size_hi != 0)) { in pcicfg_device_assign_readonly()
3237 addition.pci_size_hi = 0; in pcicfg_update_reg_prop()
3370 addition.pci_size_hi = 0; in pcicfg_update_assigned_prop_value()
4358 p.pci_size_hi = p.pci_size_low = 0; in pcicfg_fcode_probe()
5432 reg.pci_phys_mid = reg.pci_size_hi = 0; in pcicfg_probe_bridge()
5824 p.pci_size_hi = 0; in pcicfg_load_fcode()
6058 phys_spec.pci_size_hi = 0; in pcicfg_fcode_assign_bars()
6131 phys_spec.pci_size_hi = 0; in pcicfg_fcode_assign_bars()
[all …]
H A Debus.c952 rp->pci_regspec.pci_size_hi, in ebus_vreg_dump()
/titanic_50/usr/src/uts/sun4u/montecarlo/io/
H A Dacebus.c472 pci_reg.pci_size_hi, in acebus_map()
521 rp->pci_size_hi = 0; in acebus_apply_range()
/titanic_50/usr/src/uts/common/sys/
H A Dpci.h1149 uint_t pci_size_hi; /* high word of size field */ member
/titanic_50/usr/src/uts/i86pc/io/
H A Disa.c450 pci_reg_p->pci_size_hi = 0; in isa_apply_range()
485 pci_reg_p->pci_size_hi = 0; in isa_apply_range()
/titanic_50/usr/src/uts/intel/io/hotplug/pcicfg/
H A Dpcicfg.c1878 if ((reg[i].pci_size_low != 0) || (reg[i].pci_size_hi != 0)) { in pcicfg_bridge_assign()
2037 if ((reg[i].pci_size_low != 0)|| (reg[i].pci_size_hi != 0)) { in pcicfg_device_assign()
2223 (assigned[i].pci_size_hi != 0)) { in pcicfg_device_assign_readonly()
2704 (assigned[i].pci_size_hi != 0)) { in pcicfg_free_device_resources()
3064 addition.pci_size_hi = 0; in pcicfg_update_reg_prop()
3149 addition.pci_size_hi = 0; in pcicfg_update_assigned_prop_value()
/titanic_50/usr/src/uts/common/io/cardbus/
H A Dcardbus_cfg.c891 if ((reg[i].pci_size_low != 0) || (reg[i].pci_size_hi != 0)) { in cardbus_bridge_assign()
1039 if ((reg[i].pci_size_low != 0) || (reg[i].pci_size_hi != 0)) { in cardbus_isa_bridge_ranges()
2279 (assigned[i].pci_size_hi != 0)) { in cardbus_free_device_resources()
3398 addition.pci_size_hi = (uint32_t)((size>>32) & 0xffffffff);
3567 addition.pci_size_hi = 0;
/titanic_50/usr/src/uts/sun4u/io/
H A Dpmubus.c617 pci_regp->pci_size_hi = 0; in pmubus_apply_range()
H A Dsbbc.c923 rp->pci_size_hi = 0; in sbbc_apply_range()
/titanic_50/usr/src/uts/common/os/
H A Dpcifm.c1264 ((uint64_t)drv_regp[rn].pci_size_hi << 32))) { in pci_check_regs()
1289 ((uint64_t)drv_regp[rn].pci_size_hi << 32))) { in pci_check_regs()
/titanic_50/usr/src/uts/i86pc/io/gfx_private/
H A Dgfxp_vgatext.c1300 if (reg[index].pci_size_hi != 0) in vgatext_get_pci_reg_index()
/titanic_50/usr/src/uts/intel/io/vgatext/
H A Dvgatext.c1468 if (reg[index].pci_size_hi != 0) in vgatext_get_pci_reg_index()

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