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Searched refs:pci_config_get32 (Results 1 – 25 of 70) sorted by relevance

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/titanic_50/usr/src/uts/common/io/igb/
H A Digb_debug.c99 pci_config_get32(handle, PCI_CONF_BASE0)); in pci_dump()
102 pci_config_get32(handle, PCI_CONF_BASE1)); in pci_dump()
105 pci_config_get32(handle, PCI_CONF_BASE2)); in pci_dump()
108 msix_bar = pci_config_get32(handle, PCI_CONF_BASE3); in pci_dump()
114 pci_config_get32(handle, PCI_CONF_BASE4)); in pci_dump()
117 pci_config_get32(handle, PCI_CONF_BASE5)); in pci_dump()
120 pci_config_get32(handle, PCI_CONF_CIS)); in pci_dump()
129 pci_config_get32(handle, PCI_CONF_ROM)); in pci_dump()
188 pci_config_get32(handle, offset + PCI_MSI_ADDR_OFFSET)); in pci_dump()
191 pci_config_get32(handle, offset + 0x8)); in pci_dump()
[all …]
/titanic_50/usr/src/uts/common/io/ixgbe/
H A Dixgbe_debug.c224 pci_config_get32(handle, PCI_CONF_BASE0)); in ixgbe_pci_dump()
227 pci_config_get32(handle, PCI_CONF_BASE1)); in ixgbe_pci_dump()
230 pci_config_get32(handle, PCI_CONF_BASE2)); in ixgbe_pci_dump()
233 msix_bar = pci_config_get32(handle, PCI_CONF_BASE3); in ixgbe_pci_dump()
239 pci_config_get32(handle, PCI_CONF_BASE4)); in ixgbe_pci_dump()
242 pci_config_get32(handle, PCI_CONF_BASE5)); in ixgbe_pci_dump()
245 pci_config_get32(handle, PCI_CONF_CIS)); in ixgbe_pci_dump()
254 pci_config_get32(handle, PCI_CONF_ROM)); in ixgbe_pci_dump()
313 pci_config_get32(handle, offset + PCI_MSI_ADDR_OFFSET)); in ixgbe_pci_dump()
316 pci_config_get32(handle, offset + 0x8)); in ixgbe_pci_dump()
[all …]
/titanic_50/usr/src/uts/intel/io/agpgart/
H A Damd64_gart.c42 value = pci_config_get32(sc->gsoft_pcihdl, in amd64_get_aperbase()
54 value = pci_config_get32(sc->gsoft_pcihdl, AMD64_APERTURE_CONTROL); in amd64_get_apersize()
93 value = pci_config_get32(sc->gsoft_pcihdl, AMD64_GART_CACHE_CTL); in amd64_invalidate_gtlb()
107 aper_ctl = pci_config_get32(sc->gsoft_pcihdl, AMD64_APERTURE_CONTROL); in amd64_enable_gart()
109 aper_base = pci_config_get32(sc->gsoft_pcihdl, AMD64_APERTURE_BASE); in amd64_enable_gart()
110 gart_ctl = pci_config_get32(sc->gsoft_pcihdl, AMD64_GART_CACHE_CTL); in amd64_enable_gart()
111 gart_base = pci_config_get32(sc->gsoft_pcihdl, AMD64_GART_BASE); in amd64_enable_gart()
H A Dagptarget.c143 ncapid = pci_config_get32(pci_handle, nextcap); in agp_target_cap_find()
182 aper_base = pci_config_get32(softstate->tsoft_pcihdl, in agp_target_get_apbase()
556 softstate->tsoft_devid = pci_config_get32(softstate->tsoft_pcihdl, in agp_target_attach()
693 value = pci_config_get32(st->tsoft_pcihdl, cap); in agp_target_ioctl()
697 info.iagp_mode = pci_config_get32(st->tsoft_pcihdl, in agp_target_ioctl()
808 value1 = pci_config_get32(st->tsoft_pcihdl, in agp_target_ioctl()
/titanic_50/usr/src/uts/common/io/scsi/adapters/pmcs/
H A Dpmcs_fwlog.c746 pci_config_get32(pwp->pci_acc_handle, PCI_CONF_REVID)); in pmcs_dump_pcie_conf()
749 pci_config_get32(pwp->pci_acc_handle, PCI_CONF_CACHE_LINESZ)); in pmcs_dump_pcie_conf()
751 pci_config_get32(pwp->pci_acc_handle, PCI_CONF_BASE0)); in pmcs_dump_pcie_conf()
753 pci_config_get32(pwp->pci_acc_handle, PCI_CONF_BASE1)); in pmcs_dump_pcie_conf()
755 pci_config_get32(pwp->pci_acc_handle, PCI_CONF_BASE2)); in pmcs_dump_pcie_conf()
757 pci_config_get32(pwp->pci_acc_handle, PCI_CONF_BASE3)); in pmcs_dump_pcie_conf()
759 pci_config_get32(pwp->pci_acc_handle, PCI_CONF_BASE4)); in pmcs_dump_pcie_conf()
761 pci_config_get32(pwp->pci_acc_handle, PCI_CONF_BASE5)); in pmcs_dump_pcie_conf()
763 pci_config_get32(pwp->pci_acc_handle, PCI_CONF_SUBVENID)); in pmcs_dump_pcie_conf()
765 pci_config_get32(pwp->pci_acc_handle, PCI_CONF_ROM)); in pmcs_dump_pcie_conf()
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/titanic_50/usr/src/uts/common/io/
H A Dpci_cap.c94 if ((xcaps_hdr = pci_config_get32(h, base)) == PCI_CAP_EINVAL32) in pci_cap_probe()
106 if ((xcaps_hdr = pci_config_get32(h, base)) == PCI_CAP_EINVAL32) in pci_cap_probe()
181 if ((xcaps_hdr = pci_config_get32(h, base)) == PCI_CAP_EINVAL32) in pci_xcap_locate()
276 data = pci_config_get32(h, offset); in pci_cap_get()
342 if ((*ptr++ = pci_config_get32(h, base)) == PCI_CAP_EINVAL32) in pci_cap_read()
/titanic_50/usr/src/uts/common/io/e1000g/
H A De1000g_debug.c427 pci_config_get32(handle, PCI_CONF_CIS)); in pciconfig_dump()
436 pci_config_get32(handle, PCI_CONF_ROM)); in pciconfig_dump()
495 pci_config_get32(handle, offset + PCI_MSI_ADDR_OFFSET)); in pciconfig_dump()
498 pci_config_get32(handle, offset + 0x8)); in pciconfig_dump()
519 pci_config_get32(handle, offset + PCIE_DEVCAP)); in pciconfig_dump()
528 pci_config_get32(handle, offset + PCIE_LINKCAP)); in pciconfig_dump()
542 uint32_t base = pci_config_get32(handle, offset); in pciconfig_bar()
584 size = pci_config_get32(handle, offset); in pciconfig_bar()
/titanic_50/usr/src/uts/sun4u/io/pci/
H A Ddb21554.c1034 pci_config_get32(dbp->conf_handle, in db_enable_io()
1039 pci_config_get32(dbp->conf_handle, in db_enable_io()
1044 pci_config_get32(dbp->conf_handle, in db_enable_io()
1051 ((pci_config_get32(dbp->conf_handle, in db_enable_io()
1055 ((pci_config_get32(dbp->conf_handle, in db_enable_io()
1059 ((pci_config_get32(dbp->conf_handle, in db_enable_io()
1063 ((pci_config_get32(dbp->conf_handle, in db_enable_io()
1067 ((pci_config_get32(dbp->conf_handle, in db_enable_io()
1208 dvma_size[0] = pci_config_get32(dbp->conf_handle, in db_set_dvma_range()
1216 dvma_size[0] = pci_config_get32(dbp->conf_handle, in db_set_dvma_range()
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/titanic_50/usr/src/uts/common/io/cardbus/
H A Dcardbus_hp.c1695 { "BASE0 =", 0x10, (int(*)())pci_config_get32, "%s 0x%08x" },
1696 { "BASE1 =", 0x14, (int(*)())pci_config_get32, "%s 0x%08x" },
1697 { "BASE2 =", 0x18, (int(*)())pci_config_get32, "%s 0x%08x" },
1698 { "BASE3 =", 0x1c, (int(*)())pci_config_get32, "%s 0x%08x" },
1699 { "BASE4 =", 0x20, (int(*)())pci_config_get32, "%s 0x%08x" },
1700 { "CIS Pointer =", 0x28, (int(*)())pci_config_get32, "%s 0x%08x" },
1713 { "MemBase Addr=", 0x10, (int(*)())pci_config_get32, "%s 0x%08x" },
1718 { "Mem0 Base =", 0x1c, (int(*)())pci_config_get32, "%s 0x%08x" },
1719 { "Mem0 Limit =", 0x20, (int(*)())pci_config_get32, "%s 0x%08x" },
1720 { "Mem1 Base =", 0x24, (int(*)())pci_config_get32, "%s 0x%08x" },
[all …]
H A Dcardbus_cfg.c905 pci_config_get32(handle, offset), offset); in cardbus_bridge_assign()
908 pci_config_get32(handle, offset+4), in cardbus_bridge_assign()
920 request = pci_config_get32(handle, offset); in cardbus_bridge_assign()
933 pci_config_get32(handle, offset), in cardbus_bridge_assign()
940 pci_config_get32(handle, offset+4), in cardbus_bridge_assign()
946 pci_config_get32(handle, offset), in cardbus_bridge_assign()
959 pci_config_get32(handle, offset), offset); in cardbus_bridge_assign()
1145 pci_config_get32(phdl->handle, phdl->io_decode_reg)); in cardbus_add_isa_reg()
2724 request = pci_config_get32(config_handle, in cardbus_probe_children()
2807 pci_config_get32(config_handle, 0x58), in cardbus_probe_children()
[all …]
/titanic_50/usr/src/uts/common/os/
H A Dsunpci.c83 pci_config_get32(ddi_acc_handle_t handle, off_t offset) in pci_config_get32() function
467 *p = pci_config_get32(confhdl, offset);
519 chsp->chs_base0 = pci_config_get32(confhdl, PCI_CONF_BASE0);
520 chsp->chs_base1 = pci_config_get32(confhdl, PCI_CONF_BASE1);
521 chsp->chs_base2 = pci_config_get32(confhdl, PCI_CONF_BASE2);
522 chsp->chs_base3 = pci_config_get32(confhdl, PCI_CONF_BASE3);
523 chsp->chs_base4 = pci_config_get32(confhdl, PCI_CONF_BASE4);
524 chsp->chs_base5 = pci_config_get32(confhdl, PCI_CONF_BASE5);
654 *regbuf = pci_config_get32(confhdl, cap_ptr);
900 (void) pci_config_get32(confhdl, PCI_CONF_BASE5);
H A Dpcifm.c114 pcix_ecc_regs->pcix_ecc_ctlstat = pci_config_get32(erpt_p->pe_hdl, in pcix_ecc_regs_gather()
121 pcix_ecc_regs->pcix_ecc_fstaddr = pci_config_get32(erpt_p->pe_hdl, in pcix_ecc_regs_gather()
124 pcix_ecc_regs->pcix_ecc_secaddr = pci_config_get32(erpt_p->pe_hdl, in pcix_ecc_regs_gather()
127 pcix_ecc_regs->pcix_ecc_attr = pci_config_get32(( in pcix_ecc_regs_gather()
149 pcix_bdg_regs->pcix_bdg_stat = pci_config_get32(erpt_p->pe_hdl, in pcix_regs_gather()
177 pcix_regs->pcix_status = pci_config_get32(erpt_p->pe_hdl, in pcix_regs_gather()
/titanic_50/usr/src/uts/intel/io/agpmaster/
H A Dagpmaster.c342 value = pci_config_get32(pci_acc_hdl, gmadr_off); in set_gtt_mmio()
372 pci_config_get32(pci_acc_hdl, PCI_CONF_VENID); in agpmaster_attach()
470 value = pci_config_get32(softc->agpm_acc_hdl, cap); in agpmaster_ioctl()
474 info.agpi_mode = pci_config_get32( in agpmaster_ioctl()
579 ncapid = pci_config_get32(acc_handle, nextcap); in agpmaster_cap_find()
/titanic_50/usr/src/uts/intel/io/dktp/controller/ata/
H A Dsil3xxx.h89 rval = pci_config_get32(handle, PCI_CONF_BA5_IND_ACCESS); \
/titanic_50/usr/src/uts/common/io/chxge/
H A Dglue.c118 *val = pci_config_get32(obj->ch_hpci, reg); in t1_os_pci_read_config_4()
264 pe->pe_reg_val = reg = pci_config_get32(chp->ch_hpci, pe->addr); in pe_ioctl()
278 reg = pci_config_get32(chp->ch_hpci, pe->addr); in pe_ioctl()
/titanic_50/usr/src/uts/intel/io/pciex/
H A Dpcieb_x86.c497 data = (uint32_t)pci_config_get32(cfg_hdl, in pcieb_intel_serr_workaround()
503 value = (uint32_t)pci_config_get32(cfg_hdl, in pcieb_intel_serr_workaround()
592 pexctrl = pci_config_get32(bus_p->bus_cfg_hdl, in pcieb_intel_mps_workaround()
/titanic_50/usr/src/uts/intel/io/hotplug/pcicfg/
H A Dpcicfg.c419 pci_config_get32(config_handle, PCI_CONF_BASE0)); in pcicfg_dump_common_config()
421 pci_config_get32(config_handle, PCI_CONF_BASE1)); in pcicfg_dump_common_config()
433 pci_config_get32(config_handle, PCI_CONF_BASE2)); in pcicfg_dump_device_config()
435 pci_config_get32(config_handle, PCI_CONF_BASE3)); in pcicfg_dump_device_config()
437 pci_config_get32(config_handle, PCI_CONF_BASE4)); in pcicfg_dump_device_config()
439 pci_config_get32(config_handle, PCI_CONF_BASE5)); in pcicfg_dump_device_config()
441 pci_config_get32(config_handle, PCI_CONF_CIS)); in pcicfg_dump_device_config()
447 pci_config_get32(config_handle, PCI_CONF_ROM)); in pcicfg_dump_device_config()
490 pci_config_get32(config_handle, PCI_BCNF_PF_BASE_HIGH)); in pcicfg_dump_bridge_config()
492 pci_config_get32(config_handle, PCI_BCNF_PF_LIMIT_HIGH)); in pcicfg_dump_bridge_config()
[all …]
/titanic_50/usr/src/uts/intel/io/mc-amd/
H A Dmcamd_pcicfg.c84 return (pci_config_get32(hdlp->cfh_hdl, offset)); in mc_pcicfg_get32()
/titanic_50/usr/src/uts/sun4/io/
H A Dpcicfg.c448 pci_config_get32(config_handle, PCI_CONF_BASE0)); in pcicfg_dump_common_config()
450 pci_config_get32(config_handle, PCI_CONF_BASE1)); in pcicfg_dump_common_config()
462 pci_config_get32(config_handle, PCI_CONF_BASE2)); in pcicfg_dump_device_config()
464 pci_config_get32(config_handle, PCI_CONF_BASE3)); in pcicfg_dump_device_config()
466 pci_config_get32(config_handle, PCI_CONF_BASE4)); in pcicfg_dump_device_config()
468 pci_config_get32(config_handle, PCI_CONF_BASE5)); in pcicfg_dump_device_config()
470 pci_config_get32(config_handle, PCI_CONF_CIS)); in pcicfg_dump_device_config()
476 pci_config_get32(config_handle, PCI_CONF_ROM)); in pcicfg_dump_device_config()
520 pci_config_get32(config_handle, PCI_BCNF_PF_BASE_HIGH)); in pcicfg_dump_bridge_config()
522 pci_config_get32(config_handle, PCI_BCNF_PF_LIMIT_HIGH)); in pcicfg_dump_bridge_config()
[all …]
/titanic_50/usr/src/uts/intel/io/amr/
H A Damrreg.h640 #define AMR_QGET_IDB(sc) pci_config_get32(sc->regsmap_handle, \
644 #define AMR_QGET_ODB(sc) pci_config_get32(sc->regsmap_handle, \
/titanic_50/usr/src/uts/common/io/cxgbe/t4nex/
H A Dadapter.c66 *val = pci_config_get32(sc->pci_regh, reg); in t4_os_pci_read_cfg4()
/titanic_50/usr/src/uts/common/io/1394/adapters/
H A Dhci1394_attach.c585 global_swap = pci_config_get32(soft_state->pci_config, in hci1394_pci_init()
595 global_swap = pci_config_get32(soft_state->pci_config, in hci1394_pci_init()
676 global_swap = pci_config_get32(soft_state->pci_config, in hci1394_pci_resume()
/titanic_50/usr/src/uts/sun4u/io/
H A Dpmubus.c459 value = pci_config_get32(softsp->pmubus_reghdl, offset) & mask; in pmubus_get32()
557 tmp = pci_config_get32(softsp->pmubus_reghdl, offset); in pmubus_put32()
573 tmp = pci_config_get32(softsp->pmubus_reghdl, offset); in pmubus_put32()
/titanic_50/usr/src/uts/i86pc/io/pcplusmp/
H A Dapic_introp.c594 msi_pvm = pci_config_get32(handle, msi_mask_off); in apic_grp_set_cpu()
598 pci_config_get32(handle, msi_mask_off))); in apic_grp_set_cpu()
629 pci_config_get32(handle, msi_mask_off))); in apic_grp_set_cpu()
/titanic_50/usr/src/uts/common/io/ib/adapters/hermon/
H A Dhermon.c3875 state->hs_cfg_data[i] = pci_config_get32(hdl, i << 2); in hermon_sw_reset()
3895 while ((pci_config_get32(hdl, 0) & 0x0000FFFF) != PCI_VENID_MLX) { in hermon_sw_reset()
3902 pci_config_get32(hdl, 0)); in hermon_sw_reset()
4147 data32 = pci_config_get32(hdl, in hermon_pci_capability_list()
4150 data32 = pci_config_get32(hdl, in hermon_pci_capability_list()
4198 *data = pci_config_get32(hdl, vpd_data); in hermon_pci_read_vpd()
4543 msix_data = pci_config_get32(hdl, offset); in hermon_pci_capability_msix()
4548 msix_data = pci_config_get32(hdl, offset); /* table info */ in hermon_pci_capability_msix()
4554 msix_data = pci_config_get32(hdl, offset); /* PBA info */ in hermon_pci_capability_msix()
4937 pci_config_get32(pcihdl, i << 2); in hermon_quiesce()
[all …]

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