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Searched refs:pbm_ctrl_reg (Results 1 – 4 of 4) sorted by relevance

/titanic_50/usr/src/uts/sun4u/io/pci/
H A Dpcisch.c722 l = *pbm_p->pbm_ctrl_reg; /* save control register state */ in pbm_configure()
785 if (*pbm_p->pbm_ctrl_reg & XMITS_PCI_CTRL_X_MODE) in pbm_configure()
851 *pbm_p->pbm_ctrl_reg = l; in pbm_configure()
857 volatile uint64_t *ioc_csr_p = pbm_p->pbm_ctrl_reg + in pbm_configure()
876 volatile uint64_t *pbm_icd = pbm_p->pbm_ctrl_reg + in pbm_configure()
989 *pbm_p->pbm_ctrl_reg &= in pbm_disable_pci_errors()
1274 ctrl_reg_p = pbm_p->pbm_ctrl_reg; in pci_pbm_panic_callb()
1289 ctrl_reg_p = pbm_p->pbm_ctrl_reg; in pci_pbm_debug_callb()
1315 pbm_p->pbm_ctrl_reg = (uint64_t *)(a + SCHIZO_PCI_CTRL_REG_OFFSET); in pci_pbm_setup()
2249 pbm_ctl_stat = *pbm_p->pbm_ctrl_reg; in pci_check_error()
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H A Dpcipsy.c902 l = *pbm_p->pbm_ctrl_reg; /* save control register state */ in pbm_configure()
989 *pbm_p->pbm_ctrl_reg = l; in pbm_configure()
1051 *pbm_p->pbm_ctrl_reg &= in pbm_disable_pci_errors()
1278 pbm_p->pbm_ctrl_reg = (uint64_t *)(a + PSYCHO_PCI_CTRL_REG_OFFSET); in pci_pbm_setup()
1713 *pbm_p->pbm_ctrl_reg = pbm_err_p->pbm_ctl_stat; in pci_clear_error()
1881 pbm_ctl_stat = *pbm_p->pbm_ctrl_reg; in pci_check_error()
1915 pbm_err_p->pbm_ctl_stat = *pbm_p->pbm_ctrl_reg; in pci_pbm_errstate_get()
1934 pbm_ctl_stat = *pbm_p->pbm_ctrl_reg; in pbm_clear_error()
1939 pbm_ctl_stat = *pbm_p->pbm_ctrl_reg; in pbm_clear_error()
H A Dpci_pbm.c113 pbm_p->pbm_ctrl_reg, pbm_p->pbm_async_flt_status_reg, in pbm_create()
/titanic_50/usr/src/uts/sun4u/sys/pci/
H A Dpci_pbm.h85 volatile uint64_t *pbm_ctrl_reg; member