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Searched refs:pba (Results 1 – 8 of 8) sorted by relevance

/titanic_50/usr/src/uts/common/io/e1000api/
H A De1000_nvm.c948 struct e1000_pba *pba) in e1000_read_pba_raw() argument
953 if (pba == NULL) in e1000_read_pba_raw()
958 &pba->word[0]); in e1000_read_pba_raw()
963 pba->word[0] = eeprom_buf[NVM_PBA_OFFSET_0]; in e1000_read_pba_raw()
964 pba->word[1] = eeprom_buf[NVM_PBA_OFFSET_1]; in e1000_read_pba_raw()
970 if (pba->word[0] == NVM_PBA_PTR_GUARD) { in e1000_read_pba_raw()
971 if (pba->pba_block == NULL) in e1000_read_pba_raw()
984 ret_val = e1000_read_nvm(hw, pba->word[1], in e1000_read_pba_raw()
986 pba->pba_block); in e1000_read_pba_raw()
990 if (eeprom_buf_size > (u32)(pba->word[1] + in e1000_read_pba_raw()
[all …]
H A De1000_nvm.h58 struct e1000_pba *pba);
60 u32 eeprom_buf_size, struct e1000_pba *pba);
/titanic_50/usr/src/uts/common/io/ixgbe/core/
H A Dixgbe_common.c751 struct ixgbe_pba *pba) in ixgbe_read_pba_raw() argument
756 if (pba == NULL) in ixgbe_read_pba_raw()
761 &pba->word[0]); in ixgbe_read_pba_raw()
766 pba->word[0] = eeprom_buf[IXGBE_PBANUM0_PTR]; in ixgbe_read_pba_raw()
767 pba->word[1] = eeprom_buf[IXGBE_PBANUM1_PTR]; in ixgbe_read_pba_raw()
773 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) { in ixgbe_read_pba_raw()
774 if (pba->pba_block == NULL) in ixgbe_read_pba_raw()
787 ret_val = hw->eeprom.ops.read_buffer(hw, pba->word[1], in ixgbe_read_pba_raw()
789 pba->pba_block); in ixgbe_read_pba_raw()
793 if (eeprom_buf_size > (u32)(pba->word[1] + in ixgbe_read_pba_raw()
[all …]
H A Dixgbe_common.h64 struct ixgbe_pba *pba);
66 u32 eeprom_buf_size, struct ixgbe_pba *pba);
/titanic_50/usr/src/uts/common/io/igb/
H A Digb_main.c1318 uint32_t pba; in igb_init_adapter() local
1346 pba = E1000_PBA_32K; in igb_init_adapter()
1349 pba = E1000_READ_REG(hw, E1000_RXPBS); in igb_init_adapter()
1350 pba &= E1000_RXPBS_SIZE_MASK_82576; in igb_init_adapter()
1355 pba = E1000_READ_REG(hw, E1000_RXPBS); in igb_init_adapter()
1356 pba = e1000_rxpbs_adjust_82580(pba); in igb_init_adapter()
1360 pba = E1000_PBA_34K; in igb_init_adapter()
1370 pba = E1000_READ_REG(hw, E1000_PBA); in igb_init_adapter()
1371 tx_space = pba >> 16; in igb_init_adapter()
1372 pba &= 0xffff; in igb_init_adapter()
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/titanic_50/usr/src/uts/common/io/e1000g/
H A De1000g_main.c1374 uint32_t pba; in e1000g_init() local
1457 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ in e1000g_init()
1459 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ in e1000g_init()
1467 pba = E1000_PBA_30K; /* 30K for Rx, 18K for Tx */ in e1000g_init()
1469 pba = E1000_PBA_38K; /* 38K for Rx, 10K for Tx */ in e1000g_init()
1471 pba = E1000_PBA_20K; /* 20K for Rx, 12K for Tx */ in e1000g_init()
1474 pba = E1000_READ_REG(hw, E1000_PBA); in e1000g_init()
1476 pba = E1000_PBA_8K; /* 8K for Rx, 12K for Tx */ in e1000g_init()
1478 pba = E1000_PBA_10K; in e1000g_init()
1480 pba = E1000_PBA_10K; in e1000g_init()
[all …]
/titanic_50/usr/src/uts/common/io/cxgbe/t4nex/
H A Dt4_sge.c112 ddi_dma_handle_t *dma_hdl, ddi_acc_handle_t *acc_hdl, uint64_t *pba,
116 ddi_dma_handle_t *dma_hdl, ddi_acc_handle_t *acc_hdl, uint64_t *pba,
120 ddi_dma_handle_t *dma_hdl, ddi_acc_handle_t *acc_hdl, uint64_t *pba,
1785 uint64_t *pba, caddr_t *pva) in alloc_dma_memory() argument
1849 *pba = cookie.dmac_laddress; in alloc_dma_memory()
1868 uint64_t *pba, caddr_t *pva) in alloc_desc_ring() argument
1874 dma_attr, dma_hdl, acc_hdl, pba, pva)); in alloc_desc_ring()
1886 uint64_t *pba, caddr_t *pva) in alloc_tx_copybuffer() argument
1892 acc_attr, dma_attr, dma_hdl, acc_hdl, pba, pva)); in alloc_tx_copybuffer()
/titanic_50/usr/src/grub/grub-0.97/netboot/
H A De1000.c3256 uint32_t pba; local
3262 pba = E1000_PBA_48K;
3264 pba = E1000_PBA_30K;
3266 E1000_WRITE_REG(hw, PBA, pba);