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Searched refs:msr (Results 1 – 22 of 22) sorted by relevance

/titanic_50/usr/src/uts/i86pc/os/
H A Dcmi_hw.c302 #define CMI_MSRI_HASHIDX(hdl, msr) \ argument
303 (((uintptr_t)(hdl) >> 3 + (msr)) % (CMI_MSRI_HASHSZ - 1))
324 msri_addent(cmi_hdl_impl_t *hdl, uint_t msr, uint64_t val) in msri_addent() argument
326 int idx = CMI_MSRI_HASHIDX(hdl, msr); in msri_addent()
333 if (CMI_MSRI_MATCH(hep, hdl, msr)) in msri_addent()
342 hep->msrie_msrnum = msr; in msri_addent()
360 msri_lookup(cmi_hdl_impl_t *hdl, uint_t msr, uint64_t *valp) in msri_lookup() argument
362 int idx = CMI_MSRI_HASHIDX(hdl, msr); in msri_lookup()
378 if (CMI_MSRI_MATCH(hep, hdl, msr)) { in msri_lookup()
393 msri_rment(cmi_hdl_impl_t *hdl, uint_t msr) in msri_rment() argument
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H A Dmp_startup.c697 msr_warning(cpu_t *cp, const char *rw, uint_t msr, int error) in msr_warning() argument
700 cp->cpu_id, rw, msr, error); in msr_warning()
917 const uint_t msr = MSR_AMD_PATCHLEVEL; in workaround_errata() local
920 if ((err = checked_rdmsr(msr, &value)) != 0) { in workaround_errata()
921 msr_warning(cpu, "rd", msr, err); in workaround_errata()
978 const uint_t msr = MSR_AMD_HWCR; in workaround_errata() local
997 if ((error = checked_rdmsr(msr, &value)) != 0) { in workaround_errata()
998 msr_warning(cpu, "rd", msr, error); in workaround_errata()
1003 if ((error = checked_wrmsr(msr, value)) != 0) { in workaround_errata()
1004 msr_warning(cpu, "wr", msr, error); in workaround_errata()
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H A Dmachdep.c1162 checked_rdmsr(uint_t msr, uint64_t *value) in checked_rdmsr() argument
1166 *value = rdmsr(msr); in checked_rdmsr()
1175 checked_wrmsr(uint_t msr, uint64_t value) in checked_wrmsr() argument
1179 wrmsr(msr, value); in checked_wrmsr()
H A Dcms.c564 cms_msrinject(cmi_hdl_t hdl, uint_t msr, uint64_t val) in cms_msrinject() argument
569 return (CMS_OPS(cms)->cms_msrinject(hdl, msr, val)); in cms_msrinject()
/titanic_50/usr/src/uts/i86pc/io/pcplusmp/
H A Dapic_regops.c49 static uint64_t local_x2apic_read(uint32_t msr);
50 static void local_x2apic_write(uint32_t msr, uint64_t value);
157 local_x2apic_read(uint32_t msr) in local_x2apic_read() argument
161 i = (uint64_t)(rdmsr(REG_X2APIC_BASE_MSR + (msr >> 2)) & 0xffffffff); in local_x2apic_read()
166 local_x2apic_write(uint32_t msr, uint64_t value) in local_x2apic_write() argument
170 if (msr != APIC_EOI_REG) { in local_x2apic_write()
171 tmp = rdmsr(REG_X2APIC_BASE_MSR + (msr >> 2)); in local_x2apic_write()
177 wrmsr((REG_X2APIC_BASE_MSR + (msr >> 2)), tmp); in local_x2apic_write()
/titanic_50/usr/src/cmd/mdb/intel/kmdb/
H A Dkmdb_dpi_isadep.c153 kmdb_dpi_msr_get(uint_t msr) in kmdb_dpi_msr_get() argument
155 return (mdb.m_dpi->dpo_msr_get(DPI_MASTER_CPUID, msr)); in kmdb_dpi_msr_get()
159 kmdb_dpi_msr_get_by_cpu(int cpuid, uint_t msr) in kmdb_dpi_msr_get_by_cpu() argument
161 return (mdb.m_dpi->dpo_msr_get(cpuid, msr)); in kmdb_dpi_msr_get_by_cpu()
H A Dkaif.c752 kdi_msr_t *msr; in kaif_msr_get() local
758 msr = save->krs_msr; in kaif_msr_get()
760 for (i = 0; msr[i].msr_num != 0; i++) { in kaif_msr_get()
761 if (msr[i].msr_num == num && (msr[i].msr_type & KDI_MSR_READ)) in kaif_msr_get()
762 return (msr[i].kdi_msr_val); in kaif_msr_get()
H A Dkvm_cpu_amd.c56 kmt_amd_branch(uint_t cpuid, const char *label, uint_t msr) in kmt_amd_branch() argument
61 addr = (uintptr_t)kmdb_dpi_msr_get_by_cpu(cpuid, msr); in kmt_amd_branch()
H A Dkvm_isadep.c360 kmt_msr_validate(const kdi_msr_t *msr) in kmt_msr_validate() argument
364 for (/* */; msr->msr_num != 0; msr++) { in kmt_msr_validate()
365 if (kmt_rwmsr(msr->msr_num, &val, rdmsr) < 0) in kmt_msr_validate()
/titanic_50/usr/src/grub/grub-0.97/netboot/
H A Dcpu.h193 #define rdmsr(msr,val1,val2) \ argument
196 : "c" (msr))
198 #define wrmsr(msr,val1,val2) \ argument
201 : "c" (msr), "a" (val1), "d" (val2))
/titanic_50/usr/src/uts/intel/kdi/
H A Dkdi_idt.c289 kdi_msr_add_clrentry(uint_t msr) in kdi_msr_add_clrentry() argument
313 bcopy(&msr, patch, sizeof (uint32_t)); in kdi_msr_add_clrentry()
321 kdi_msr_add_wrexit(uint_t msr, uint64_t *valp) in kdi_msr_add_wrexit() argument
323 kdi_msr_wrexit_msr = msr; in kdi_msr_add_wrexit()
/titanic_50/usr/src/uts/sun4/io/
H A Dsu_driver.c129 static void asy_ppsevent(struct asycom *asy, int msr);
1916 asy_ppsevent(struct asycom *asy, int msr) in asy_ppsevent() argument
1920 if ((msr & DCD) == 0) in asy_ppsevent()
1926 } else if (msr & DCD) { in asy_ppsevent()
1979 int msr; in async_msint() local
1981 msr = INB(MSR); /* this resets the interrupt */ in async_msint()
1982 asy->asy_cached_msr = msr; in async_msint()
1987 (msr & DCTS) ? "CTS" : " ", in async_msint()
1988 (msr & DDSR) ? "DSR" : " ", in async_msint()
1989 (msr & DRI) ? "RI " : " ", in async_msint()
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/titanic_50/usr/src/uts/intel/pcbe/
H A Dcore_pcbe.c174 #define WRMSR(msr, value) \ argument
175 wrmsr((msr), (value)); \
176 DTRACE_PROBE2(wrmsr, uint64_t, (msr), uint64_t, (value));
178 #define RDMSR(msr, value) \ argument
179 (value) = rdmsr((msr)); \
180 DTRACE_PROBE2(rdmsr, uint64_t, (msr), uint64_t, (value));
/titanic_50/usr/src/uts/common/sys/usb/clients/usbser/usbser_keyspan/
H A Dusa90msg.h163 uint8_t msr; /* reports the actual MSR register */ member
/titanic_50/usr/src/uts/common/io/
H A Dasy.c2359 asy_ppsevent(struct asycom *asy, int msr) in asy_ppsevent() argument
2363 if ((msr & DCD) == 0) in asy_ppsevent()
2369 } else if (msr & DCD) { in asy_ppsevent()
2565 int msr, t_cflag = async->async_ttycommon.t_cflag; in async_msint() local
2572 msr = ddi_get8(asy->asy_iohandle, asy->asy_ioaddr + MSR); in async_msint()
2579 (msr & DCTS) ? "DCTS" : " ", in async_msint()
2580 (msr & DDSR) ? "DDSR" : " ", in async_msint()
2581 (msr & DRI) ? "DRI " : " ", in async_msint()
2582 (msr & DDCD) ? "DDCD" : " ", in async_msint()
2583 (msr & CTS) ? "CTS " : " ", in async_msint()
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/titanic_50/usr/src/uts/i86pc/ml/
H A Dcpr_wakecode.s150 movl $MSR_AMD_GSBASE, %ecx / save gsbase msr
155 movl $MSR_AMD_KGSBASE, %ecx / save kgsbase msr
709 movl $MSR_AMD_GSBASE, %ecx / restore gsbase msr
714 movl $MSR_AMD_KGSBASE, %ecx / restore kgsbase msr
/titanic_50/usr/src/uts/i86pc/cpu/amd_opteron/
H A Dao_mca.c756 ao_ms_msrinject(cmi_hdl_t hdl, uint_t msr, uint64_t val) in ao_ms_msrinject() argument
762 if (cmi_hdl_wrmsr(hdl, msr, val) == CMI_SUCCESS) in ao_ms_msrinject()
/titanic_50/usr/src/uts/common/io/usb/clients/usbser/usbftdi/
H A Duftdi_dsd.c1655 uint8_t msr = FTDI_GET_MSR(data->b_rptr); in uftdi_bulkin_cb() local
1663 if (uf->uf_msr != msr) { in uftdi_bulkin_cb()
1669 uf->uf_msr, msr); in uftdi_bulkin_cb()
1671 uf->uf_msr = msr; in uftdi_bulkin_cb()
/titanic_50/usr/src/uts/common/io/usb/clients/usbser/usbser_keyspan/
H A Dkeyspan_pipe.c1438 if (status_msg->msr & USA_MSR_dCTS || in keyspan_status_cb_usa19hs()
1439 status_msg->msr & USA_MSR_dDSR || in keyspan_status_cb_usa19hs()
1440 status_msg->msr & USA_MSR_dRI || in keyspan_status_cb_usa19hs()
1441 status_msg->msr & USA_MSR_dDCD) { in keyspan_status_cb_usa19hs()
/titanic_50/usr/src/uts/i86pc/cpu/authenticamd/
H A Dauthamd_main.c1110 authamd_msrinject(cmi_hdl_t hdl, uint_t msr, uint64_t val) in authamd_msrinject() argument
1116 if (cmi_hdl_wrmsr(hdl, msr, val) == CMI_SUCCESS) in authamd_msrinject()
/titanic_50/usr/src/uts/i86pc/cpu/generic_cpu/
H A Dgcpu_mca.c1996 uint_t msr = regs[i].cmr_msrnum; in gcpu_msrinject() local
2000 if (cms_msrinject(hdl, msr, val) != CMS_SUCCESS) in gcpu_msrinject()
2003 errs += (cmi_hdl_wrmsr(hdl, msr, val) != CMI_SUCCESS); in gcpu_msrinject()
/titanic_50/usr/src/uts/common/io/rtw/
H A Drtw.c1638 uint8_t msr; in rtw_set_nettype() local
1643 msr = RTW_READ8(&rsc->sc_regs, RTW_MSR) & ~RTW_MSR_NETYPE_MASK; in rtw_set_nettype()
1648 msr |= RTW_MSR_NETYPE_ADHOC_OK; in rtw_set_nettype()
1651 msr |= RTW_MSR_NETYPE_AP_OK; in rtw_set_nettype()
1654 msr |= RTW_MSR_NETYPE_INFRA_OK; in rtw_set_nettype()
1657 RTW_WRITE8(&rsc->sc_regs, RTW_MSR, msr); in rtw_set_nettype()