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Searched refs:msi_state (Results 1 – 11 of 11) sorted by relevance

/titanic_50/usr/src/uts/sun4/io/px/
H A Dpx_msi.c79 msi_state_p->msi_p[i].msi_state = MSI_STATE_FREE; in px_msi_attach()
155 if (msi_state_p->msi_p[i].msi_state in px_msi_alloc()
185 msi_state_p->msi_p[i].msi_state = MSI_STATE_INUSE; in px_msi_alloc()
200 if (msi_state_p->msi_p[i].msi_state == MSI_STATE_FREE) { in px_msi_alloc()
221 if (msi_state_p->msi_p[i].msi_state != MSI_STATE_FREE) in px_msi_alloc()
223 msi_state_p->msi_p[i].msi_state = MSI_STATE_INUSE; in px_msi_alloc()
270 msi_state_p->msi_p[i].msi_state = MSI_STATE_FREE; in px_msi_free()
H A Dpx_tools.c133 pci_msi_valid_state_t msi_state; in pxtool_get_intr() local
145 &msi_state) != DDI_SUCCESS) || in pxtool_get_intr()
146 (msi_state != PCI_MSI_VALID)) in pxtool_get_intr()
294 pci_msi_valid_state_t msi_state; in pxtool_set_intr() local
305 &msi_state) != DDI_SUCCESS) || in pxtool_set_intr()
306 (msi_state != PCI_MSI_VALID)) in pxtool_set_intr()
H A Dpx_msi.h39 uint_t msi_state; /* MSI alloc state */ member
H A Dpx_lib.h137 pci_msi_state_t *msi_state);
139 pci_msi_state_t msi_state);
H A Dpx_ib.c929 pci_msi_state_t msi_state; in px_ib_set_msix_target() local
1050 &msi_state)) != DDI_SUCCESS) { in px_ib_set_msix_target()
1058 if (msi_state == PCI_MSI_STATE_DELIVERED) { in px_ib_set_msix_target()
/titanic_50/usr/src/uts/sun4v/io/px/
H A Dpx_lib4v.h176 pci_msi_state_t *msi_state);
178 pci_msi_state_t msi_state);
H A Dpx_hcall.s163 pci_msi_state_t *msi_state)
169 pci_msi_state_t msi_state)
H A Dpx_lib4v.c1090 pci_msi_state_t *msi_state) in px_lib_msi_getstate() argument
1098 msi_num, msi_state)) != H_EOK) { in px_lib_msi_getstate()
1105 *msi_state); in px_lib_msi_getstate()
1113 pci_msi_state_t msi_state) in px_lib_msi_setstate() argument
1118 "msi_state 0x%x\n", dip, msi_num, msi_state); in px_lib_msi_setstate()
1121 msi_num, msi_state)) != H_EOK) { in px_lib_msi_setstate()
/titanic_50/usr/src/uts/sun4u/io/px/
H A Dpx_lib4u.h369 pci_msi_state_t *msi_state);
371 pci_msi_state_t msi_state);
H A Dpx_lib4u.c1182 pci_msi_state_t *msi_state) in px_lib_msi_getstate() argument
1190 msi_num, msi_state)) != H_EOK) { in px_lib_msi_getstate()
1197 *msi_state); in px_lib_msi_getstate()
1205 pci_msi_state_t msi_state) in px_lib_msi_setstate() argument
1210 "msi_state 0x%x\n", dip, msi_num, msi_state); in px_lib_msi_setstate()
1213 msi_num, msi_state)) != H_EOK) { in px_lib_msi_setstate()
H A Dpx_hlib.c2479 pci_msi_state_t *msi_state) in hvio_msi_getstate() argument
2481 *msi_state = CSRA_BR((caddr_t)dev_hdl, MSI_MAPPING, in hvio_msi_getstate()
2489 pci_msi_state_t msi_state) in hvio_msi_setstate() argument
2493 switch (msi_state) { in hvio_msi_setstate()