| /titanic_50/usr/src/uts/common/io/nxge/npi/ |
| H A D | npi_fflp.c | 237 (tctl.bits.ldw.stat != TCAM_CTL_RWC_RWC_STAT)) { in npi_fflp_tcam_check_completion()
257 (tctl.bits.ldw.match != TCAM_CTL_RWC_RWC_MATCH)) { in npi_fflp_tcam_check_completion()
314 tctl.bits.ldw.location = location; in npi_fflp_tcam_entry_invalidate()
315 tctl.bits.ldw.rwc = TCAM_CTL_RWC_TCAM_WR; in npi_fflp_tcam_entry_invalidate()
361 tctl.bits.ldw.rwc = TCAM_CTL_RWC_TCAM_CMP; in npi_fflp_tcam_entry_match()
373 if (tctl_stat.bits.ldw.match == TCAM_CTL_RWC_RWC_MATCH) { in npi_fflp_tcam_entry_match()
374 return (uint32_t)(tctl_stat.bits.ldw.location); in npi_fflp_tcam_entry_match()
406 tctl.bits.ldw.location = location; in npi_fflp_tcam_entry_read()
407 tctl.bits.ldw.rwc = TCAM_CTL_RWC_TCAM_RD; in npi_fflp_tcam_entry_read()
476 tctl.bits.ldw.location = location; in npi_fflp_tcam_entry_write()
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| H A D | npi_rxdma.c | 242 page_vld.bits.ldw.page0 = 0; in npi_rxdma_cfg_logical_page_disable()
245 page_vld.bits.ldw.page1 = 0; in npi_rxdma_cfg_logical_page_disable()
286 page_vld.bits.ldw.page0 = 0; in npi_rxdma_cfg_logical_page()
289 page_vld.bits.ldw.page1 = 0; in npi_rxdma_cfg_logical_page()
298 page_vld.bits.ldw.page0 = 1; in npi_rxdma_cfg_logical_page()
305 page_vld.bits.ldw.page1 = 1; in npi_rxdma_cfg_logical_page()
309 page_vld.bits.ldw.func = pg_cfg->func_num; in npi_rxdma_cfg_logical_page()
316 page_mask.bits.ldw.mask = pg_cfg->mask >> LOG_PAGE_ADDR_SHIFT; in npi_rxdma_cfg_logical_page()
317 page_value.bits.ldw.value = pg_cfg->value >> LOG_PAGE_ADDR_SHIFT; in npi_rxdma_cfg_logical_page()
318 page_reloc.bits.ldw.relo = pg_cfg->reloc >> LOG_PAGE_ADDR_SHIFT; in npi_rxdma_cfg_logical_page()
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| H A D | npi_zcp.c | 324 val.qw0.bits.ldw.rdc_tbl_offset = in npi_zcp_tt_static_entry()
325 sflow->qw0.bits.ldw.rdc_tbl_offset; in npi_zcp_tt_static_entry()
329 val.qw0.bits.ldw.buf_size = in npi_zcp_tt_static_entry()
330 sflow->qw0.bits.ldw.buf_size; in npi_zcp_tt_static_entry()
334 val.qw0.bits.ldw.num_buf = sflow->qw0.bits.ldw.num_buf; in npi_zcp_tt_static_entry()
338 val.qw0.bits.ldw.ulp_end = sflow->qw0.bits.ldw.ulp_end; in npi_zcp_tt_static_entry()
342 val.qw1.bits.ldw.ulp_end = sflow->qw1.bits.ldw.ulp_end; in npi_zcp_tt_static_entry()
346 val.qw1.bits.ldw.ulp_end_en = in npi_zcp_tt_static_entry()
347 sflow->qw1.bits.ldw.ulp_end_en; in npi_zcp_tt_static_entry()
351 val.qw1.bits.ldw.unmap_all_en = in npi_zcp_tt_static_entry()
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| H A D | npi_vir.c | 296 if (!sr.bits.ldw.tas) { in npi_dev_func_sr_init()
302 if (!sr.bits.ldw.sr) { in npi_dev_func_sr_init()
304 sr.bits.ldw.sr |= NPI_DEV_SR_LOCK_ST_FREE; in npi_dev_func_sr_init()
306 sr.bits.ldw.tas = 0; in npi_dev_func_sr_init()
313 sr.bits.ldw.sr)); in npi_dev_func_sr_init()
318 sr.bits.ldw)); in npi_dev_func_sr_init()
319 status = NPI_VIR_TAS_BUSY(sr.bits.ldw.funcid); in npi_dev_func_sr_init()
350 if (!sr.bits.ldw.tas) { in npi_dev_func_sr_lock_enter()
355 state = sr.bits.ldw.sr & NPI_DEV_SR_LOCK_ST_MASK; in npi_dev_func_sr_lock_enter()
361 sr.bits.ldw.sr |= (NPI_DEV_SR_LOCK_ST_BUSY | in npi_dev_func_sr_lock_enter()
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| H A D | npi_txdma.c | 264 mode32.bits.ldw.mode32 = 1; in npi_txdma_mode32_set()
266 mode32.bits.ldw.mode32 = 0; in npi_txdma_mode32_set()
328 vld.bits.ldw.func = cfgp->func_num; in npi_txdma_log_page_set()
353 vld.bits.ldw.func, in npi_txdma_log_page_set()
406 vld.bits.ldw.func = cfgp->func_num; in npi_txdma_log_page_get()
415 cfgp->func_num = vld.bits.ldw.func; in npi_txdma_log_page_get()
424 cfgp->valid = vld.bits.ldw.page0; in npi_txdma_log_page_get()
432 cfgp->valid = vld.bits.ldw.page1; in npi_txdma_log_page_get()
938 cs.bits.ldw.rst = 1; in npi_txdma_channel_control()
953 cs.bits.ldw.rst = 1; in npi_txdma_channel_control()
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| H A D | npi_txc.c | 434 cntl.bits.ldw.txc_enabled = 1; in npi_txc_global_enable()
461 cntl.bits.ldw.txc_enabled = 0; in npi_txc_global_disable()
872 if ((ecc.bits.ldw.correct_error) || (ecc.bits.ldw.uncorrect_error)) { in npi_txc_ro_states_get()
889 ecc.bits.ldw.ecc_address = 0; in npi_txc_ro_states_get()
890 ecc.bits.ldw.correct_error = 0; in npi_txc_ro_states_get()
891 ecc.bits.ldw.uncorrect_error = 0; in npi_txc_ro_states_get()
892 ecc.bits.ldw.clr_st = 1; in npi_txc_ro_states_get()
912 ctl.bits.ldw.clr_fail_state = 1; in npi_txc_ro_states_get()
961 if ((ecc.bits.ldw.correct_error) || (ecc.bits.ldw.uncorrect_error)) { in npi_txc_sf_states_get()
972 ecc.bits.ldw.ecc_address = 0; in npi_txc_sf_states_get()
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| H A D | npi_rxdma.h | 190 uint32_t ldw; member
192 uint32_t ldw;
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| H A D | npi_zcp.h | 119 } while ((ram_ctl.bits.ldw.busy != 0) && (cnt > 0));\
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| /titanic_50/usr/src/uts/common/io/nxge/ |
| H A D | nxge_txc.c | 204 if (txc_control.bits.ldw.txc_enabled == 0) { in nxge_txc_tdc_bind()
348 if (istatus.bits.ldw.port0_int_status) { in nxge_txc_handle_sys_errors()
351 err_status = istatus.bits.ldw.port0_int_status; in nxge_txc_handle_sys_errors()
355 if (istatus.bits.ldw.port1_int_status) { in nxge_txc_handle_sys_errors()
358 err_status = istatus.bits.ldw.port1_int_status; in nxge_txc_handle_sys_errors()
362 if (istatus.bits.ldw.port2_int_status) { in nxge_txc_handle_sys_errors()
365 err_status = istatus.bits.ldw.port2_int_status; in nxge_txc_handle_sys_errors()
369 if (istatus.bits.ldw.port3_int_status) { in nxge_txc_handle_sys_errors()
372 err_status = istatus.bits.ldw.port3_int_status; in nxge_txc_handle_sys_errors()
490 istatus.bits.ldw.port0_int_status = err_status; in nxge_txc_handle_port_errors()
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| H A D | nxge_zcp.c | 336 zcps.bits.ldw.rrfifo_urun = 1; in nxge_zcp_inject_err()
338 zcps.bits.ldw.rspfifo_uc_err = 1; in nxge_zcp_inject_err()
340 zcps.bits.ldw.stat_tbl_perr = 1; in nxge_zcp_inject_err()
342 zcps.bits.ldw.dyn_tbl_perr = 1; in nxge_zcp_inject_err()
344 zcps.bits.ldw.buf_tbl_perr = 1; in nxge_zcp_inject_err()
348 zcps.bits.ldw.cfifo_ecc0 = 1; in nxge_zcp_inject_err()
351 zcps.bits.ldw.cfifo_ecc1 = 1; in nxge_zcp_inject_err()
354 zcps.bits.ldw.cfifo_ecc2 = 1; in nxge_zcp_inject_err()
357 zcps.bits.ldw.cfifo_ecc3 = 1; in nxge_zcp_inject_err()
364 zcps.bits.ldw.rrfifo_orun = 1; in nxge_zcp_inject_err()
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| H A D | nxge_txdma.c | 961 head_index = tx_head.bits.ldw.head; in nxge_txdma_reclaim()
962 head_wrap = tx_head.bits.ldw.wrap; in nxge_txdma_reclaim()
1180 if (!rs && cs.bits.ldw.mk) { in nxge_tx_intr()
1270 intr_dbg.bits.ldw.nack_pref = 1; in nxge_txdma_channel_disable()
1451 intr_dbg.bits.ldw.nack_pref = 1; in nxge_txdma_stop_inj_err()
1803 head_index = tx_head.bits.ldw.head; in nxge_txdma_channel_hung()
1804 head_wrap = tx_head.bits.ldw.wrap; in nxge_txdma_channel_hung()
1988 intr_dbg.bits.ldw.nack_pref = 1; in nxge_txdma_fixup_hung_channel()
2119 printf("\n\thead index %d", hdl.bits.ldw.head); in nxge_txdma_regs_dump()
2122 printf("\n\ttail index %d\n", kick.bits.ldw.tail); in nxge_txdma_regs_dump()
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| H A D | nxge_fm.c | 632 if (hash_log.bits.ldw.pio_err) { in nxge_fm_ereport()
724 zcp_stats.errlog.state_mach.bits.ldw.state; in nxge_fm_ereport()
801 bits.ldw.ecc_address, in nxge_fm_ereport()
804 bits.ldw.ro_ecc_data0, in nxge_fm_ereport()
807 bits.ldw.ro_ecc_data1, in nxge_fm_ereport()
810 bits.ldw.ro_ecc_data2, in nxge_fm_ereport()
813 bits.ldw.ro_ecc_data3, in nxge_fm_ereport()
816 bits.ldw.ro_ecc_data4, in nxge_fm_ereport()
848 bits.ldw.ecc_address, in nxge_fm_ereport()
851 bits.ldw.sf_ecc_data0, in nxge_fm_ereport()
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| H A D | nxge_rxdma.c | 584 rdc_desc.rcr_threshold = cfgb_p->bits.ldw.pthres; in nxge_enable_rxdma_channel()
590 rdc_desc.rcr_timeout = cfgb_p->bits.ldw.timeout; in nxge_enable_rxdma_channel()
591 rdc_desc.rcr_timeout_enable = cfgb_p->bits.ldw.entout; in nxge_enable_rxdma_channel()
1148 entry_p->bits.ldw.pkt_buf_addr)); in nxge_dump_rcr_entry()
1185 printf("nxge_rxdma_regs_dump: rbr len %d \n", rbr_stat.bits.ldw.qlen); in nxge_rxdma_regs_dump()
1842 mgm.bits.ldw.arm = 1; in nxge_rx_intr()
1843 mgm.bits.ldw.timer = ldgp->ldg_timer; in nxge_rx_intr()
1906 mgm.bits.ldw.arm = 0; in nxge_rx_intr()
1924 mgm.bits.ldw.arm = 1; in nxge_rx_intr()
1925 mgm.bits.ldw.timer = ldgp->ldg_timer; in nxge_rx_intr()
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| H A D | nxge_fzc.c | 355 red.bits.ldw.win = RXDMA_RED_WINDOW_DEFAULT; in nxge_init_fzc_rdc()
356 red.bits.ldw.thre = in nxge_init_fzc_rdc()
358 red.bits.ldw.win_syn = RXDMA_RED_WINDOW_DEFAULT; in nxge_init_fzc_rdc()
359 red.bits.ldw.thre_sync = in nxge_init_fzc_rdc()
364 red.bits.ldw.thre_sync, in nxge_init_fzc_rdc()
365 red.bits.ldw.thre_sync)); in nxge_init_fzc_rdc()
549 cfg.valid = rbrp->page_valid.bits.ldw.page0; in nxge_init_fzc_rxdma_channel_pages()
563 cfg.valid = rbrp->page_valid.bits.ldw.page1; in nxge_init_fzc_rxdma_channel_pages()
575 rbrp->page_hdl.bits.ldw.handle); in nxge_init_fzc_rxdma_channel_pages()
600 red.bits.ldw.win = RXDMA_RED_WINDOW_DEFAULT; in nxge_init_fzc_rxdma_channel_red()
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| H A D | nxge_fflp.c | 1504 tcam_ptr.match_action.bits.ldw.rdctbl = rdc_grp; in nxge_add_tcam_entry()
1505 tcam_ptr.match_action.bits.ldw.offset = offset; in nxge_add_tcam_entry()
1506 tcam_ptr.match_action.bits.ldw.tres = in nxge_add_tcam_entry()
1509 tcam_ptr.match_action.bits.ldw.disc = 1; in nxge_add_tcam_entry()
1571 tcam_ptr.match_action.bits.ldw.rdctbl = nxgep->class_config.mac_rdcgrp; in nxge_tcam_handle_ip_fragment()
1572 tcam_ptr.match_action.bits.ldw.offset = 0; /* use the default */ in nxge_tcam_handle_ip_fragment()
1573 tcam_ptr.match_action.bits.ldw.tres = in nxge_tcam_handle_ip_fragment()
2164 if (vlan_err.bits.ldw.m_err || vlan_err.bits.ldw.err) { in nxge_fflp_handle_sys_errors()
2168 portn, vlan_err.bits.ldw.addr, in nxge_fflp_handle_sys_errors()
2169 vlan_err.bits.ldw.data)); in nxge_fflp_handle_sys_errors()
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| H A D | nxge_hw.c | 431 if (estat.bits.ldw.smx) { in nxge_syserr_intr()
435 } else if (estat.bits.ldw.mac) { in nxge_syserr_intr()
444 } else if (estat.bits.ldw.ipp) { in nxge_syserr_intr()
448 } else if (estat.bits.ldw.zcp) { in nxge_syserr_intr()
453 } else if (estat.bits.ldw.tdmc) { in nxge_syserr_intr()
461 } else if (estat.bits.ldw.rdmc) { in nxge_syserr_intr()
466 } else if (estat.bits.ldw.txc) { in nxge_syserr_intr()
470 } else if ((nxgep->niu_type != N2_NIU) && estat.bits.ldw.peu) { in nxge_syserr_intr()
474 } else if (estat.bits.ldw.meta1) { in nxge_syserr_intr()
478 } else if (estat.bits.ldw.meta2) { in nxge_syserr_intr()
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| H A D | nxge_intr.c | 1091 mgm.bits.ldw.arm = 1; in nxge_hio_ldgimgn()
1092 mgm.bits.ldw.timer = group->ldg_timer; in nxge_hio_ldgimgn()
1094 mgm.bits.ldw.arm = 0; in nxge_hio_ldgimgn()
1095 mgm.bits.ldw.timer = 0; in nxge_hio_ldgimgn()
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| H A D | nxge_send.c | 763 sop_tx_desc_p->bits.ldw.sad = dma_ioaddr & 0xffffffff; in nxge_start()
772 tmp_desc_p->bits.ldw.sad = dma_ioaddr & 0xffffffff; in nxge_start()
1010 kick.bits.ldw.wrap = in nxge_start()
1012 kick.bits.ldw.tail = in nxge_start()
1055 kick.bits.ldw.wrap = tx_ring_p->wr_index_wrap; in nxge_start()
1056 kick.bits.ldw.tail = (uint16_t)tx_ring_p->wr_index; in nxge_start()
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| /titanic_50/usr/src/uts/common/sys/nxge/ |
| H A D | nxge_hw.h | 106 } ldw; member
134 } ldw; member
183 } ldw; member
232 } ldw; member
265 uint32_t ldw; member
293 } ldw; member
331 } ldw; member
364 } ldw; member
391 } ldw; member
430 } ldw; member
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| H A D | nxge_txc_hw.h | 57 } ldw; member
78 } ldw; member
117 } ldw; member
147 } ldw; member
182 } ldw; member
210 } ldw; member
235 } ldw; member
262 } ldw; member
302 } ldw; member
329 } ldw; member
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| H A D | nxge_zcp_hw.h | 97 } ldw; member
142 } ldw; member
205 } ldw; member
249 } ldw; member
270 } ldw; member
324 } ldw; member
355 } ldw; member
378 } ldw; member
399 } ldw; member
420 } ldw; member
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| H A D | nxge_txdma_hw.h | 87 } ldw; member
138 } ldw; member
220 } ldw; member
261 } ldw; member
290 } ldw; member
359 } ldw; member
459 } ldw; member
499 } ldw; member
526 } ldw; member
551 } ldw; member
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| H A D | nxge_rxdma_hw.h | 58 } ldw; member
97 } ldw; member
118 } ldw; member
151 } ldw; member
185 } ldw; member
218 } ldw; member
278 } ldw; member
343 } ldw; member
388 } ldw; member
428 } ldw; member
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| H A D | nxge_fflp_hw.h | 97 } ldw; member
127 } ldw; member
164 } ldw; member
264 } ldw; member
324 } ldw; member
367 } ldw; member
445 } ldw; member
477 } ldw; member
516 } ldw; member
543 } ldw; member
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