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/titanic_50/usr/src/uts/sun4u/io/
H A Dpanther_asm.s81 #define PN_ECACHE_REFLUSH_LINE(l2_index, l3_index, scr2, scr3) \ argument
85 ldxa [l2_index + scr2]ASI_L2_TAG, %g0; \
/titanic_50/usr/src/uts/sun4u/cpu/
H A Dus3_cheetahplus_asm.s102 #define PN_ECACHE_REFLUSH_LINE(l2_index, l3_index, scr2, scr3) \ argument
106 ldxa [l2_index + scr2]ASI_L2_TAG, %g0; \