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Searched refs:intr_cnt (Results 1 – 25 of 42) sorted by relevance

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/titanic_50/usr/src/uts/common/io/chxge/
H A Dsge.c178 cmn_err(CE_NOTE, "&sge->intr_cnt: %p\n", &sge->intr_cnt); in t1_sge_create()
244 sge->intr_cnt.arp_sent++; in t1_espi_workaround()
362 sge->intr_cnt.tx_soft_cksums++; in sge_data_out()
371 sge->intr_cnt.tx_soft_cksums++; in sge_data_out()
382 sge->intr_cnt.tx_reclaims[qid]++; in sge_data_out()
393 sge->intr_cnt.cmdQ_full[qid]++; in sge_data_out()
408 sge->intr_cnt.tx_descs[MBLK_MAX - 1]++; in sge_data_out()
410 sge->intr_cnt.tx_descs[count]++; in sge_data_out()
554 sge->intr_cnt.respQ_empty++; in t1_sge_intr_error_handler()
556 sge->intr_cnt.respQ_overflow++; in t1_sge_intr_error_handler()
[all …]
H A Dpe.c336 sa->sge->intr_cnt.tx_need_cpl_space++; in pe_start()
365 sa->sge->intr_cnt.tx_multi_mblks++; in pe_start()
418 sa->sge->intr_cnt.tx_no_dvma1++; in pe_start()
423 sa->sge->intr_cnt.tx_no_dma1++; in pe_start()
448 sa->sge->intr_cnt.tx_no_dma1++; in pe_start()
471 sa->sge->intr_cnt.tx_no_dma1++; in pe_start()
516 sa->sge->intr_cnt.tx_no_dvma2++; in pe_start()
521 sa->sge->intr_cnt.tx_no_dma2++; in pe_start()
534 sa->sge->intr_cnt.tx_no_dma2++; in pe_start()
547 sa->sge->intr_cnt.tx_no_dma2++; in pe_start()
H A Dch.c1751 chp->sge->intr_cnt.tx_msg_pullups++; in ch_send()
1758 chp->sge->intr_cnt.tx_hdr_pullups++; in ch_send()
1773 chp->sge->intr_cnt.tx_udp_ip_frag++; in ch_send()
1776 chp->sge->intr_cnt.tx_tcp_ip_frag++; in ch_send()
H A Dsge.h416 struct sge_intr_counts intr_cnt; member
/titanic_50/usr/src/uts/common/io/chxge/com/
H A Despi.c34 struct espi_intr_counts intr_cnt; member
163 espi->intr_cnt.DIP4_err++; in t1_espi_intr_handler()
165 espi->intr_cnt.rx_drops++; in t1_espi_intr_handler()
167 espi->intr_cnt.tx_drops++; in t1_espi_intr_handler()
169 espi->intr_cnt.rx_ovflw++; in t1_espi_intr_handler()
171 espi->intr_cnt.parity_err++; in t1_espi_intr_handler()
173 espi->intr_cnt.DIP2_parity_err++; in t1_espi_intr_handler()
189 return &espi->intr_cnt; in t1_espi_get_intr_counts()
H A Dmc3.c39 struct pemc3_intr_counts intr_cnt; member
122 mc3->intr_cnt.corr_err++; in t1_mc3_intr_handler()
135 mc3->intr_cnt.uncorr_err++; in t1_mc3_intr_handler()
148 mc3->intr_cnt.parity_err++; in t1_mc3_intr_handler()
154 mc3->intr_cnt.addr_err++; in t1_mc3_intr_handler()
365 return &mc3->intr_cnt; in t1_mc3_get_intr_counts()
H A Dmc4.c38 struct pemc4_intr_counts intr_cnt; member
252 mc4->intr_cnt.corr_err++; in t1_mc4_intr_handler()
265 mc4->intr_cnt.uncorr_err++; in t1_mc4_intr_handler()
278 mc4->intr_cnt.addr_err++; in t1_mc4_intr_handler()
291 return &mc4->intr_cnt; in t1_mc4_get_intr_counts()
/titanic_50/usr/src/uts/common/io/xge/drv/
H A Dxge.c796 if (avail < lldev->intr_cnt) { in xge_alloc_intrs()
798 "%d available", lldev->intr_cnt, avail); in xge_alloc_intrs()
803 lldev->intr_table_size = lldev->intr_cnt * sizeof (ddi_intr_handle_t); in xge_alloc_intrs()
808 lldev->intr_cnt, &actual, intr_behavior); in xge_alloc_intrs()
818 if (lldev->intr_cnt != actual) { in xge_alloc_intrs()
860 for (i = 0; i < lldev->intr_cnt; i++) { in xge_free_intrs()
919 for (i = 0; i < lldev->intr_cnt; i++) { in xge_add_intrs()
969 for (i = 0; i < lldev->intr_cnt; i++) { in xge_add_intrs()
991 lldev->intr_cnt)) != DDI_SUCCESS) { in xge_enable_intrs()
998 for (i = 0; i < lldev->intr_cnt; i++) { in xge_enable_intrs()
[all …]
H A Dxgell.h380 int intr_cnt; member
/titanic_50/usr/src/uts/common/io/scsi/adapters/pmcs/
H A Dpmcs_attach.c868 switch (pwp->intr_cnt) { in pmcs_attach()
1330 pwp->intr_cnt = 0; in pmcs_unattach()
2259 pwp->intr_cnt); in pmcs_disable_intrs()
2355 pwp->intr_cnt = 0; in pmcs_setup_intr_impl()
2360 pwp->intr_cnt = actual; in pmcs_setup_intr_impl()
2426 if (pwp->intr_cnt == 0) { in pmcs_setup_intr()
2432 iv_table_size = sizeof (ddi_intr_handler_t *) * pwp->intr_cnt; in pmcs_setup_intr()
2438 switch (pwp->intr_cnt) { in pmcs_setup_intr()
2454 "%s: intr_cnt = %d - unexpected", __func__, pwp->intr_cnt); in pmcs_setup_intr()
2459 for (i = 0; i < pwp->intr_cnt; i++) { in pmcs_setup_intr()
[all …]
/titanic_50/usr/src/uts/common/io/ixgbe/
H A Dixgbe_main.c1503 for (i = 0; i < ixgbe->intr_cnt; i++) { in ixgbe_chip_start()
1970 int, ixgbe->intr_cnt); in ixgbe_cbfunc()
2000 ixgbe->intr_cnt + count > ixgbe->intr_cnt_max) || in ixgbe_intr_adjust()
2002 ixgbe->intr_cnt - count < ixgbe->intr_cnt_min)) in ixgbe_intr_adjust()
2045 DDI_INTR_TYPE_MSIX, ixgbe->intr_cnt, count, &actual, in ixgbe_intr_adjust()
2053 ixgbe->intr_cnt += count; in ixgbe_intr_adjust()
2057 for (i = ixgbe->intr_cnt - count; in ixgbe_intr_adjust()
2058 i < ixgbe->intr_cnt; i ++) { in ixgbe_intr_adjust()
2068 ixgbe->intr_cnt -= count; in ixgbe_intr_adjust()
2141 ixgbe->intr_cnt, ixgbe->intr_cnt_min, ixgbe->intr_cnt_max); in ixgbe_intr_adjust()
[all …]
H A Dixgbe_debug.c66 for (i = 0; i < ixgbe->intr_cnt; i++) { in ixgbe_dump_interrupt()
/titanic_50/usr/src/cmd/nvmeadm/
H A Dnvmeadm.c778 int intr_cnt; in do_get_feat_intr_vect() local
780 intr_cnt = nvme_intr_cnt(fd); in do_get_feat_intr_vect()
782 if (intr_cnt == -1) in do_get_feat_intr_vect()
787 for (arg = 0; arg < intr_cnt; arg++) { in do_get_feat_intr_vect()
/titanic_50/usr/src/uts/common/io/rge/
H A Drge_main.c1341 rgep->intr_cnt = actual; in rge_add_intrs()
1412 (void) ddi_intr_block_disable(rgep->htable, rgep->intr_cnt); in rge_rem_intrs()
1414 for (i = 0; i < rgep->intr_cnt; i++) { in rge_rem_intrs()
1420 for (i = 0; i < rgep->intr_cnt; i++) { in rge_rem_intrs()
1786 (void) ddi_intr_block_enable(rgep->htable, rgep->intr_cnt); in rge_attach()
1789 for (i = 0; i < rgep->intr_cnt; i++) { in rge_attach()
H A Drge.h391 int intr_cnt; /* # of intrs count returned */ member
/titanic_50/usr/src/uts/common/io/igb/
H A Digb_main.c1501 for (i = 0; i < igb->intr_cnt; i++) in igb_init_adapter()
4492 igb->intr_cnt = 0; in igb_alloc_intr_handles()
4510 igb->intr_cnt = actual; in igb_alloc_intr_handles()
4691 ASSERT(vector == igb->intr_cnt); in igb_add_intr_handlers()
4750 ASSERT(vector == igb->intr_cnt); in igb_setup_msix_82575()
4848 ASSERT(vector == igb->intr_cnt); in igb_setup_msix_82576()
4938 ASSERT(vector == igb->intr_cnt); in igb_setup_msix_82580()
4950 for (i = 0; i < igb->intr_cnt; i++) { in igb_rem_intr_handlers()
4968 for (i = 0; i < igb->intr_cnt; i++) { in igb_rem_intrs()
4992 rc = ddi_intr_block_enable(igb->htable, igb->intr_cnt); in igb_enable_intrs()
[all …]
/titanic_50/usr/src/uts/sun4u/io/pci/
H A Dpcisch.c258 int intr_len, intr_cnt, ret; in pci_intr_setup() local
265 intr_cnt = BYTES_TO_1275_CELLS(intr_len); in pci_intr_setup()
266 if (intr_cnt < CBNINTR_CDMA) /* CBNINTR_CDMA is 0 based */ in pci_intr_setup()
270 if (intr_cnt == CBNINTR_CDMA) in pci_intr_setup()
271 intr_cnt++; in pci_intr_setup()
273 new_intr_buf = kmem_alloc(CELLS_1275_TO_BYTES(intr_cnt), KM_SLEEP); in pci_intr_setup()
279 pci_p->pci_inos_len = CELLS_1275_TO_BYTES(intr_cnt); in pci_intr_setup()
282 (int *)new_intr_buf, intr_cnt)) in pci_intr_setup()
287 cb_p->cb_no_of_inos = intr_cnt; in pci_intr_setup()
/titanic_50/usr/src/uts/common/io/skd/
H A Dskd.c4174 skdev->intr_cnt = actual; in skd_setup_intr()
4215 skdev->intr_cnt)) != DDI_SUCCESS) { in skd_setup_intr()
4224 for (i = 0; i < skdev->intr_cnt; i++) { in skd_setup_intr()
4262 skdev->intr_cnt)) != DDI_SUCCESS) { in skd_disable_intr()
4268 for (i = 0; i < skdev->intr_cnt; i++) { in skd_disable_intr()
4294 Dcmn_err(CE_CONT, "REL_INTR intr_cnt=%d", skdev->intr_cnt); in skd_release_intr()
4316 if (i < skdev->intr_cnt) { in skd_release_intr()
4340 skdev->intr_cnt = 0; in skd_release_intr()
H A Dskd.h427 int32_t intr_cnt; member
/titanic_50/usr/src/uts/common/io/fibre-channel/fca/qlge/
H A Dqlge.c886 for (i = 0; i < qlge->intr_cnt; i++) { in ql_enable_all_completion_interrupts()
907 for (i = 0; i < qlge->intr_cnt; i++) { in ql_disable_all_completion_interrupts()
3918 for (vector = 0; vector < qlge->intr_cnt; vector++) { in ql_add_intr_handlers()
3986 qlge->intr_cnt)); in ql_add_intr_handlers()
3987 (void) ddi_intr_block_enable(qlge->htable, qlge->intr_cnt); in ql_add_intr_handlers()
3989 for (i = 0; i < qlge->intr_cnt; i++) { in ql_add_intr_handlers()
4018 for (i = 0; i < qlge->intr_cnt; i++, intr_ctx++) { in ql_resolve_queues_to_irqs()
4065 i = qlge->intr_cnt; in ql_resolve_queues_to_irqs()
4146 qlge->intr_cnt); in ql_free_irq_vectors()
4148 for (i = 0; i < qlge->intr_cnt; i++) { in ql_free_irq_vectors()
[all …]
/titanic_50/usr/src/uts/common/io/aac/
H A Daac.h490 int intr_cnt; /* # of intrs count returned */ member
/titanic_50/usr/src/uts/common/sys/scsi/adapters/pmcs/
H A Dpmcs.h565 int intr_cnt; member
/titanic_50/usr/src/uts/common/io/myri10ge/drv/
H A Dmyri10ge_var.h444 int intr_cnt; member
/titanic_50/usr/src/uts/common/io/comstar/port/qlt/
H A Dqlt.h286 int intr_cnt; member
/titanic_50/usr/src/uts/common/io/bge/
H A Dbge_main2.c4423 bgep->intr_cnt = actual;
4487 for (i = 0; i < bgep->intr_cnt; i++) {
4492 kmem_free(bgep->htable, bgep->intr_cnt * sizeof (ddi_intr_handle_t));
4503 (void) ddi_intr_block_enable(bgep->htable, bgep->intr_cnt);
4506 for (i = 0; i < bgep->intr_cnt; i++) {
4520 (void) ddi_intr_block_disable(bgep->htable, bgep->intr_cnt);
4522 for (i = 0; i < bgep->intr_cnt; i++) {

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