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Searched refs:inl (Results 1 – 25 of 40) sorted by relevance

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/titanic_50/usr/src/lib/libkmf/libkmf/common/
H A Dpem_encode.c142 unsigned char *in, int inl) in PEM_EncodeUpdate() argument
148 if (inl == 0) in PEM_EncodeUpdate()
150 if ((ctx->num+inl) < ctx->length) { in PEM_EncodeUpdate()
151 (void) memcpy(&(ctx->enc_data[ctx->num]), in, inl); in PEM_EncodeUpdate()
152 ctx->num += inl; in PEM_EncodeUpdate()
159 inl -= i; in PEM_EncodeUpdate()
168 while (inl >= ctx->length) { in PEM_EncodeUpdate()
171 inl -= ctx->length; in PEM_EncodeUpdate()
178 if (inl != 0) in PEM_EncodeUpdate()
179 (void) memcpy(&(ctx->enc_data[0]), in, inl); in PEM_EncodeUpdate()
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/titanic_50/usr/src/grub/grub-0.97/netboot/
H A Dsis900.c210 if(inl(ee_addr) & EEGNT) { in sis96x_get_mac_addr()
282 rfcrSave = inl(rfcr + ioaddr); in sis635_get_mac_addr()
363 outl(ACCESSMODE | inl(ioaddr + cr), ioaddr + cr); in sis900_probe()
431 #define eeprom_delay() inl(ee_addr)
474 retval = (retval << 1) | ((inl(ee_addr) & EEDO) ? 1 : 0); in sis900_read_eeprom()
486 #define sis900_mdio_delay() inl(mdio_addr)
537 retval = (retval << 1) | ((inl(mdio_addr) & MDIO) ? 1 : 0); in sis900_mdio_read()
612 outl(RxENA| inl(ioaddr + cr), ioaddr + cr); in sis900_init()
635 outl(RxRESET | TxRESET | RESET | inl(ioaddr + cr), ioaddr + cr); in sis900_reset()
639 status ^= (inl(isr + ioaddr) & status); in sis900_reset()
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H A Dnatsemi.c295 u32 chip_config = inl(ioaddr + ChipConfig); in natsemi_probe()
304 nic_name, (int)inl(ioaddr + 0x84), advertising); in natsemi_probe()
312 SavedClkRun = inl(ioaddr + ClkRun); in natsemi_probe()
333 #define eeprom_delay(ee_addr) inl(ee_addr)
372 retval |= (inl(ee_addr) & EE_DataOut) ? 1 << i : 0; in eeprom_read()
391 return inl(ioaddr + 0x80 + (location<<2)) & 0xffff; in mdio_read()
427 if (inl(ioaddr + ChipConfig) & 0x20000000) { /* Full duplex */ in natsemi_init()
462 if (inl(ioaddr + SiliconRev) == 0x302) { in natsemi_reset()
515 inl(ioaddr + TxRingPtr)); in natsemi_init_txd()
549 inl(ioaddr + RxRingPtr)); in natsemi_init_rxd()
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H A Ddavicom.c97 #define eeprom_delay() inl(ee_addr)
317 phy_data=(inl(ee_addr)>>19) & 0x1; in phy_read_1bit()
414 retval = (retval << 1) | ((inl(ee_addr) & EE_DATA_READ) ? 1 : 0); in read_eeprom()
482 outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6); in davicom_reset()
509 outl(inl(ioaddr + CSR6) | 0x00002000, ioaddr + CSR6); in davicom_reset()
530 outl(inl(ioaddr + CSR6) | 0x00000002, ioaddr + CSR6); in davicom_reset()
629 outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6); in davicom_disable()
632 (volatile unsigned long)inl(ioaddr + CSR8); in davicom_disable()
676 outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6); in davicom_probe()
679 (volatile unsigned long)inl(ioaddr + CSR8); in davicom_probe()
H A Dtulip.c361 #define eeprom_delay() inl(ee_addr)
549 #define mdio_delay() inl(mdio_addr)
580 inl(ioaddr + 0xA0); in mdio_read()
581 inl(ioaddr + 0xA0); in mdio_read()
583 if ( ! ((retval = inl(ioaddr + 0xA0)) & 0x80000000)) in mdio_read()
591 return inl(ioaddr + 0xB4 + (location<<2)); in mdio_read()
593 return inl(ioaddr + 0xD0); in mdio_read()
595 return inl(ioaddr + 0xD4 + ((location-29)<<2)); in mdio_read()
620 retval = (retval << 1) | ((inl(mdio_addr) & MDIO_DATA_READ) ? 1 : 0); in mdio_read()
641 if ( ! (inl(ioaddr + 0xA0) & 0x80000000)) in mdio_write()
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H A Dsundance.c412 outl(inl(BASE + ASICCtrl) | 0x0c, BASE + ASICCtrl); in sundance_reset()
440 sdc->nic_name, (int) inl(BASE + RxStatus), in sundance_reset()
441 (int) inw(BASE + TxStatus), (int) inl(BASE + MACCtrl0), in sundance_reset()
680 if (inl(BASE + ASICCtrl) & 0x80) { in sundance_probe()
705 dprintf(("ASIC Control is %x.\n", inl(BASE + ASICCtrl))); in sundance_probe()
707 dprintf(("ASIC Control is now %x.\n", inl(BASE + ASICCtrl))); in sundance_probe()
H A Dpcnet32.c350 return (inl(addr + PCNET32_DWIO_RDP) & 0xffff); in pcnet32_dwio_read_csr()
362 return (inl(addr + PCNET32_DWIO_BDP) & 0xffff); in pcnet32_dwio_read_bcr()
373 return (inl(addr + PCNET32_DWIO_RAP) & 0xffff); in pcnet32_dwio_read_rap()
383 inl(addr + PCNET32_DWIO_RESET); in pcnet32_dwio_reset()
389 return ((inl(addr + PCNET32_DWIO_RAP) & 0xffff) == 88); in pcnet32_dwio_check()
H A D3c90x.c402 cfg = inl(INF_3C90X.IOAddr + regInternalConfig_3_l); in a3c90x_reset()
525 while(inl(INF_3C90X.IOAddr + regDnListPtr_l) != 0) in a3c90x_transmit()
912 cfg = inl(INF_3C90X.IOAddr + regInternalConfig_3_l); in a3c90x_probe()
H A D3c595.c373 vx_connector = (inl(BASE + VX_W3_INTERNAL_CFG) in vxgetlink()
413 j = inl(BASE + VX_W3_INTERNAL_CFG) & ~INTERNAL_CONNECTOR_MASK; in vxsetlink()
H A Depic100.c478 retval = (retval << 1) | ((inl(eectl) & EE_DATA_READ) ? 1 : 0); in read_eeprom()
502 if ((inl(mmctl) & MII_READOP) == 0) in mii_read()
H A Drtl8139.c249 #define eeprom_delay() inl(ee_addr)
406 txstatus = inl(nic->ioaddr+ TxStatus0 + cur_tx*4); in rtl_transmit()
H A Deepro100.c295 val = inl(ioaddr + SCBCtrlMDI); in mdio_write()
316 val = inl(ioaddr + SCBCtrlMDI); in mdio_read()
/titanic_50/usr/src/ucblib/libucb/port/gen/
H A Dnlist.c154 struct nlist *inl; in _elf_nlist() local
160 for (inl = list, nreq = 0; inl->n_name && inl->n_name[0]; ++inl, nreq++) in _elf_nlist()
366 struct nlist *p, *inl; in _coff_nlist() local
389 for (inl = list, nreq = 0; inl->n_name && inl->n_name[0]; ++inl, nreq++) in _coff_nlist()
/titanic_50/usr/src/uts/i86pc/os/
H A Dpci_neptune.c73 if ((inl(PCI_CADDR2(0, PCI_CONF_VENID)) != 0x04a38086) || in pci_check_neptune()
94 tmp = inl(PCI_CONFADD); in pci_check_neptune()
106 if (inl(PCI_CONFDATA) != ((0x04a3 << 16) | 0x8086)) { in pci_check_neptune()
H A Dpci_mech1.c92 val = inl(PCI_CONFDATA); in pci_mech1_getl()
H A Dpci_mech2.c114 val = inl(PCI_CADDR2(device, reg)); in pci_mech2_getl()
H A Dpci_mech1_amd.c140 val = inl(PCI_CONFDATA); in pci_mech1_amd_getl()
/titanic_50/usr/src/uts/i86pc/ml/
H A Damd64.il137 .inline inl,4
140 inl (%dx)
H A Dia32.il124 .inline inl,4
127 inl (%dx)
/titanic_50/usr/src/uts/intel/asm/
H A Dsunddi.h68 inl(int port) in inl() function
/titanic_50/usr/src/uts/intel/ia32/os/
H A Dddi_i86.c522 return (ddi_swap32(inl((uintptr_t)addr))); in i_ddi_io_swap_get32()
689 *h++ = ddi_swap32(inl(port)); in i_ddi_io_swap_rep_get32()
692 *h++ = ddi_swap32(inl(port)); in i_ddi_io_swap_rep_get32()
1030 val = inl((uintptr_t)addr); in i_ddi_prot_io_get32()
1090 val = ddi_swap32(inl((uintptr_t)addr)); in i_ddi_prot_io_swap_get32()
1295 if ((*h++ = inl(port)) == 0xffffffff) in i_ddi_prot_io_rep_get32()
1299 if ((*h++ = inl(port)) == 0xffffffff) in i_ddi_prot_io_rep_get32()
1479 if ((*h++ = ddi_swap32(inl(port))) == 0xffffffff) in i_ddi_prot_io_swap_rep_get32()
1483 if ((*h++ = ddi_swap32(inl(port))) == 0xffffffff) in i_ddi_prot_io_swap_rep_get32()
/titanic_50/usr/src/cmd/mdb/intel/amd64/kmdb/
H A Dkmdb_asmutil.s145 4: inl (%dx)
/titanic_50/usr/src/uts/intel/sys/
H A Darchsystm.h104 extern uint32_t inl(int port);
/titanic_50/usr/src/uts/intel/ia32/ml/
H A Dddi_i86_asm.s407 inl (%dx)
436 inl (%dx)
1089 inl (%dx)
1097 inl (%dx)
1468 inl (%dx)
1502 inl (%dx)
H A Di86_subr.s1504 inl(int port_address)
1511 ENTRY(inl)
1514 inl (%dx)
1516 SET_SIZE(inl)
1520 ENTRY(inl)
1522 inl (%dx)
1524 SET_SIZE(inl)
1543 D16 inl (%dx)
1552 D16 inl (%dx)
4379 inl (%dx)
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