| /titanic_50/usr/src/uts/sun4/io/px/ |
| H A D | px_ib.c | 44 static void px_ib_cpu_ticks_to_ih_nsec(px_ib_t *ib_p, px_ih_t *ih_p,
257 px_ib_cpu_ticks_to_ih_nsec(px_ib_t *ib_p, px_ih_t *ih_p, uint32_t cpu_id) in px_ib_cpu_ticks_to_ih_nsec() argument
276 ticks = atomic_swap_64(&ih_p->ih_ticks, 0); in px_ib_cpu_ticks_to_ih_nsec()
277 ih_p->ih_nsec += (uint64_t)tick2ns(ticks, cpu_id); in px_ib_cpu_ticks_to_ih_nsec()
485 px_ib_new_ino_pil(px_ib_t *ib_p, devino_t ino_num, uint_t pil, px_ih_t *ih_p) in px_ib_new_ino_pil() argument
495 ih_p->ih_next = ih_p; in px_ib_new_ino_pil()
497 ipil_p->ipil_ih_head = ih_p; in px_ib_new_ino_pil()
498 ipil_p->ipil_ih_tail = ih_p; in px_ib_new_ino_pil()
499 ipil_p->ipil_ih_start = ih_p; in px_ib_new_ino_pil()
600 px_ib_ino_add_intr(px_t *px_p, px_ino_pil_t *ipil_p, px_ih_t *ih_p) in px_ib_ino_add_intr() argument
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| H A D | px_intr.c | 74 px_ih_t *ih_p; in px_spurintr() local
105 for (i = 0, ih_p = ipil_p->ipil_ih_start; in px_spurintr()
106 i < ipil_p->ipil_ih_size; i++, ih_p = ih_p->ih_next) in px_spurintr()
107 cmn_err(CE_CONT, "!%s-%d#%x ", NAMEINST(ih_p->ih_dip), in px_spurintr()
108 ih_p->ih_inum); in px_spurintr()
149 px_ih_t *ih_p = ipil_p->ipil_ih_start; in px_intx_intr() local
159 for (i = 0; i < ipil_p->ipil_ih_size; i++, ih_p = ih_p->ih_next) { in px_intx_intr()
160 dev_info_t *dip = ih_p->ih_dip; in px_intx_intr()
161 uint_t (*handler)() = ih_p->ih_handler; in px_intx_intr()
162 caddr_t arg1 = ih_p->ih_handler_arg1; in px_intx_intr()
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| H A D | px_ib.h | 145 uint_t pil, px_ih_t *ih_p);
147 extern int px_ib_ino_add_intr(px_t *px_p, px_ino_pil_t *ipil_p, px_ih_t *ih_p);
148 extern int px_ib_ino_rem_intr(px_t *px_p, px_ino_pil_t *ipil_p, px_ih_t *ih_p);
156 extern void px_ib_free_ih(px_ih_t *ih_p);
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| /titanic_50/usr/src/uts/sun4u/opl/io/pcicmu/ |
| H A D | pcmu_intr.c | 70 ih_t *ih_p = ino_p->pino_ih_start; in pcmu_spurintr() local
98 for (i = 0; i < ino_p->pino_ih_size; i++, ih_p = ih_p->ih_next) { in pcmu_spurintr()
99 cmn_err(CE_CONT, "!%s-%d#%x ", NAMEINST(ih_p->ih_dip), in pcmu_spurintr()
100 ih_p->ih_inum); in pcmu_spurintr()
129 ih_t *ih_p = ino_p->pino_ih_start; in pcmu_intr_wrapper() local
136 for (i = 0; i < ino_p->pino_ih_size; i++, ih_p = ih_p->ih_next) { in pcmu_intr_wrapper()
137 dev_info_t *dip = ih_p->ih_dip; in pcmu_intr_wrapper()
138 uint_t (*handler)() = ih_p->ih_handler; in pcmu_intr_wrapper()
139 caddr_t arg1 = ih_p->ih_handler_arg1; in pcmu_intr_wrapper()
140 caddr_t arg2 = ih_p->ih_handler_arg2; in pcmu_intr_wrapper()
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| H A D | pcmu_ib.c | 440 pcmu_ib_new_ino(pcmu_ib_t *pib_p, pcmu_ib_ino_t ino_num, ih_t *ih_p) in pcmu_ib_new_ino() argument
456 ih_p->ih_next = ih_p; in pcmu_ib_new_ino()
457 ino_p->pino_ih_head = ih_p; in pcmu_ib_new_ino()
458 ino_p->pino_ih_tail = ih_p; in pcmu_ib_new_ino()
459 ino_p->pino_ih_start = ih_p; in pcmu_ib_new_ino()
496 pcmu_ib_ino_add_intr(pcmu_t *pcmu_p, pcmu_ib_ino_info_t *ino_p, ih_t *ih_p) in pcmu_ib_ino_add_intr() argument
549 ih_p->ih_next = ino_p->pino_ih_head; in pcmu_ib_ino_add_intr()
550 ino_p->pino_ih_tail->ih_next = ih_p; in pcmu_ib_ino_add_intr()
551 ino_p->pino_ih_tail = ih_p; in pcmu_ib_ino_add_intr()
584 pcmu_ib_ino_rem_intr(pcmu_t *pcmu_p, pcmu_ib_ino_info_t *ino_p, ih_t *ih_p) in pcmu_ib_ino_rem_intr() argument
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| /titanic_50/usr/src/uts/sun4u/io/pci/ |
| H A D | pci_intr.c | 223 ih_t *ih_p = ipil_p->ipil_ih_start; in pci_spurintr() local
258 for (i = 0; i < ipil_p->ipil_ih_size; i++, ih_p = ih_p->ih_next) in pci_spurintr()
259 cmn_err(CE_CONT, "!%s-%d#%x ", NAMEINST(ih_p->ih_dip), in pci_spurintr()
260 ih_p->ih_inum); in pci_spurintr()
297 ih_t *ih_p = ipil_p->ipil_ih_start; in pci_intr_wrapper() local
300 for (i = 0; i < ipil_p->ipil_ih_size; i++, ih_p = ih_p->ih_next) { in pci_intr_wrapper()
301 dev_info_t *dip = ih_p->ih_dip; in pci_intr_wrapper()
302 uint_t (*handler)() = ih_p->ih_handler; in pci_intr_wrapper()
303 caddr_t arg1 = ih_p->ih_handler_arg1; in pci_intr_wrapper()
304 caddr_t arg2 = ih_p->ih_handler_arg2; in pci_intr_wrapper()
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| H A D | pci_ib.c | 253 ib_cpu_ticks_to_ih_nsec(ib_t *ib_p, ih_t *ih_p, uint32_t cpu_id) in ib_cpu_ticks_to_ih_nsec() argument
272 ticks = atomic_swap_64(&ih_p->ih_ticks, 0); in ib_cpu_ticks_to_ih_nsec()
273 ih_p->ih_nsec += (uint64_t)tick2ns(ticks, cpu_id); in ib_cpu_ticks_to_ih_nsec()
539 ib_new_ino_pil(ib_t *ib_p, ib_ino_t ino_num, uint_t pil, ih_t *ih_p) in ib_new_ino_pil() argument
559 ih_p->ih_next = ih_p; in ib_new_ino_pil()
561 ipil_p->ipil_ih_head = ih_p; in ib_new_ino_pil()
562 ipil_p->ipil_ih_tail = ih_p; in ib_new_ino_pil()
563 ipil_p->ipil_ih_start = ih_p; in ib_new_ino_pil()
656 ib_ino_add_intr(pci_t *pci_p, ib_ino_pil_t *ipil_p, ih_t *ih_p) in ib_ino_add_intr() argument
692 ih_p->ih_next = ipil_p->ipil_ih_head; in ib_ino_add_intr()
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| /titanic_50/usr/src/uts/sun4v/io/niumx/ |
| H A D | niumx.c | 204 niumx_ih_t *ih_p = niumxds_p->niumx_ihtable; in niumx_intr_dist() local
208 for (i = 0; i < NIUMX_MAX_INTRS; i++, ih_p++) { in niumx_intr_dist()
209 niusysino_t sysino = ih_p->ih_sysino; in niumx_intr_dist()
213 dev_info_t *dip = ih_p->ih_dip; in niumx_intr_dist()
215 if (!sysino || (cpuid = intr_dist_cpuid()) == ih_p->ih_cpuid) in niumx_intr_dist()
228 ih_p->ih_inum, sysino); in niumx_intr_dist()
236 if (ih_p->ih_state == HV_INTR_VALID) in niumx_intr_dist()
241 ih_p->ih_cpuid = cpuid; in niumx_intr_dist()
252 niumx_ih_t *ih_p; in niumx_attach() local
287 ih_p = niumxds_p->niumx_ihtable; in niumx_attach()
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| /titanic_50/usr/src/uts/i86pc/io/pci/ |
| H A D | pci_kstats.c | 77 ddi_intr_handle_impl_t tmp_hdl, *ih_p = private_data->hdlp; in pci_ih_ks_update() local
78 dev_info_t *dip = ih_p->ih_dip; in pci_ih_ks_update()
104 bcopy(ih_p, &tmp_hdl, sizeof (ddi_intr_handle_impl_t)); in pci_ih_ks_update()
110 if ((ih_p->ih_state != DDI_IHDL_STATE_ENABLE) || in pci_ih_ks_update()
134 switch (ih_p->ih_type) { in pci_ih_ks_update()
145 pci_ks_template.ihks_pil.value.ui64 = ih_p->ih_pri; in pci_ih_ks_update()
147 ((ihdl_plat_t *)ih_p->ih_private)->ip_ticks; in pci_ih_ks_update()
149 pci_ks_template.ihks_cookie.value.ui64 = ih_p->ih_vector; in pci_ih_ks_update()
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| /titanic_50/usr/src/uts/sun4u/sys/pci/ |
| H A D | pci_ib.h | 207 ih_t *ih_p);
211 extern void ib_ino_add_intr(pci_t *pci_p, ib_ino_pil_t *ipil_p, ih_t *ih_p);
212 extern void ib_ino_rem_intr(pci_t *pci_p, ib_ino_pil_t *ipil_p, ih_t *ih_p);
218 extern void ib_free_ih(ih_t *ih_p);
229 extern void ib_cpu_ticks_to_ih_nsec(ib_t *ib_p, ih_t *ih_p, uint32_t cpu_id);
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| /titanic_50/usr/src/uts/sun4u/opl/sys/pcicmu/ |
| H A D | pcmu_ib.h | 150 pcmu_ib_ino_t ino_num, ih_t *ih_p);
156 pcmu_ib_ino_info_t *ino_p, ih_t *ih_p);
158 pcmu_ib_ino_info_t *ino_p, ih_t *ih_p);
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