Home
last modified time | relevance | path

Searched refs:gcr (Results 1 – 8 of 8) sorted by relevance

/titanic_50/usr/src/uts/common/io/audio/drv/audio810/
H A Daudio810.c1402 uint32_t gcr; in audio810_chip_init() local
1408 gcr = I810_BM_GET32(I810_REG_GCR); in audio810_chip_init()
1416 gcr &= ~(I810_GCR_ACLINK_OFF | I810_GCR_SIS_CHANNELS_MASK); in audio810_chip_init()
1418 gcr &= ~(I810_GCR_ACLINK_OFF | I810_GCR_CHANNELS_MASK); in audio810_chip_init()
1429 gcr |= (gcr & I810_GCR_COLD_RST) == 0 ? in audio810_chip_init()
1431 I810_BM_PUT32(I810_REG_GCR, gcr); in audio810_chip_init()
1436 gcr = I810_BM_GET32(I810_REG_GCR); in audio810_chip_init()
1437 if ((gcr & I810_GCR_WARM_RST) == 0) { in audio810_chip_init()
1486 uint32_t gcr; in audio810_set_channels() local
1495 gcr = I810_BM_GET32(I810_REG_GCR); in audio810_set_channels()
[all …]
/titanic_50/usr/src/uts/i86pc/io/
H A Dhpet_acpi.c416 uint64_t gcr; in hpet_start_main_counter() local
419 gcr = *gcr_ptr; in hpet_start_main_counter()
421 gcr |= HPET_GCFR_ENABLE_CNF; in hpet_start_main_counter()
422 *gcr_ptr = gcr; in hpet_start_main_counter()
423 gcr = *gcr_ptr; in hpet_start_main_counter()
425 return (gcr & HPET_GCFR_ENABLE_CNF ? AE_OK : ~AE_OK); in hpet_start_main_counter()
432 uint64_t gcr; in hpet_stop_main_counter() local
435 gcr = *gcr_ptr; in hpet_stop_main_counter()
437 gcr &= ~HPET_GCFR_ENABLE_CNF; in hpet_stop_main_counter()
438 *gcr_ptr = gcr; in hpet_stop_main_counter()
[all …]
/titanic_50/usr/src/uts/common/io/ixgbe/core/
H A Dixgbe_82598.c82 u32 gcr = IXGBE_READ_REG(hw, IXGBE_GCR); in ixgbe_set_pcie_completion_timeout() local
86 if (gcr & IXGBE_GCR_CMPL_TMOUT_MASK) in ixgbe_set_pcie_completion_timeout()
93 if (!(gcr & IXGBE_GCR_CAP_VER2)) { in ixgbe_set_pcie_completion_timeout()
94 gcr |= IXGBE_GCR_CMPL_TMOUT_10ms; in ixgbe_set_pcie_completion_timeout()
108 gcr &= ~IXGBE_GCR_CMPL_TMOUT_RESEND; in ixgbe_set_pcie_completion_timeout()
109 IXGBE_WRITE_REG(hw, IXGBE_GCR, gcr); in ixgbe_set_pcie_completion_timeout()
/titanic_50/usr/src/uts/common/io/nxge/
H A Dnxge_mac.c4798 mii_gcr_t gcr; in nxge_mii_xcvr_init() local
5011 gcr.value = 0; in nxge_mii_xcvr_init()
5012 gcr.bits.ms_mode_en = in nxge_mii_xcvr_init()
5014 gcr.bits.master = in nxge_mii_xcvr_init()
5016 gcr.bits.link_1000fdx = in nxge_mii_xcvr_init()
5018 gcr.bits.link_1000hdx = in nxge_mii_xcvr_init()
5022 (uint8_t)(uint32_t)(&mii_regs->gcr), in nxge_mii_xcvr_init()
5024 (uint8_t)(uint64_t)(&mii_regs->gcr), in nxge_mii_xcvr_init()
5026 gcr.value)) != NXGE_OK) in nxge_mii_xcvr_init()
5045 gcr.value = 0; in nxge_mii_xcvr_init()
[all …]
/titanic_50/usr/src/uts/common/io/e1000api/
H A De1000_mac.c2059 u32 gcr; in e1000_set_pcie_no_snoop_generic() local
2067 gcr = E1000_READ_REG(hw, E1000_GCR); in e1000_set_pcie_no_snoop_generic()
2068 gcr &= ~(PCIE_NO_SNOOP_ALL); in e1000_set_pcie_no_snoop_generic()
2069 gcr |= no_snoop; in e1000_set_pcie_no_snoop_generic()
2070 E1000_WRITE_REG(hw, E1000_GCR, gcr); in e1000_set_pcie_no_snoop_generic()
H A De1000_82575.c2228 u32 gcr = E1000_READ_REG(hw, E1000_GCR); in e1000_set_pcie_completion_timeout() local
2233 if (gcr & E1000_GCR_CMPL_TMOUT_MASK) in e1000_set_pcie_completion_timeout()
2240 if (!(gcr & E1000_GCR_CAP_VER2)) { in e1000_set_pcie_completion_timeout()
2241 gcr |= E1000_GCR_CMPL_TMOUT_10ms; in e1000_set_pcie_completion_timeout()
2261 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND; in e1000_set_pcie_completion_timeout()
2263 E1000_WRITE_REG(hw, E1000_GCR, gcr); in e1000_set_pcie_completion_timeout()
/titanic_50/usr/src/uts/common/sys/nxge/
H A Dnxge_mii.h69 uchar_t gcr; /* Gigabit basic mode control register. */ member
/titanic_50/usr/src/uts/common/io/nxge/npi/
H A Dnpi_mac.c3367 mii_gcr_t gcr; in npi_mac_pcs_mii_write() local
3389 gcr.value = value; in npi_mac_pcs_mii_write()
3390 pcs_anar.bits.w0.full_duplex = gcr.bits.link_1000fdx; in npi_mac_pcs_mii_write()
3391 pcs_anar.bits.w0.half_duplex = gcr.bits.link_1000hdx; in npi_mac_pcs_mii_write()