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/titanic_50/usr/src/cmd/mdb/sparc/v9/kmdb/
H A Dkaif_startup.s55 set kaif_cpusave_getaddr, %g6; \
57 jmp %g6; \
125 * %g6 - cpusave area
132 add %g6, KRS_GREGS + GREG_KREGS, %g5
135 stx %g2, [%g6 + KRS_TSTATE]
159 stx %g6, [%o5 + KREG_OFF(KREG_G6)]
180 set kaif_cpusave_getaddr, %g6
181 jmp %g6
184 add %g6, KRS_GREGS + GREG_KREGS, %g5
187 ADD_CRUMB(%g6, KRM_PC, %g4, %g1)
[all …]
H A Dkaif_resume.s75 mov %l6, %g6
82 add %g6, KRS_FPREGS, %g4 ! %g4 = &cpusave[this_cpuid].krs_fpregs
105 ldx [%g6 + KRS_RWINS], %g3 ! %g3 = &cpusave[this_cpuid].krs_wins
142 ldx [%g6 + KRS_MMU_PCONTEXT], %g4
147 ldx [%g6 + KRS_TSTATE], %g4
172 ldx [%g5 + KREG_OFF(KREG_G6)], %g6
H A Dkaif_invoke.s62 kreg_t g6, kreg_t g7)
139 mov %g6, %l0
140 mov %i3, %g6 ! Restore PROC_REG for kernel call
148 mov %l0, %g6
/titanic_50/usr/src/uts/sun4u/ml/
H A Dmach_interrupt.s130 TRACE_PTR(%g4, %g6)
131 GET_TRACE_TICK(%g6, %g3)
132 stxa %g6, [%g4 + TRAP_ENT_TICK]%asi
133 rdpr %tl, %g6
134 stha %g6, [%g4 + TRAP_ENT_TL]%asi
135 rdpr %tt, %g6
136 stha %g6, [%g4 + TRAP_ENT_TT]%asi
137 rdpr %tpc, %g6
138 stna %g6, [%g4 + TRAP_ENT_TPC]%asi
139 rdpr %tstate, %g6
[all …]
H A Dmach_xc.s77 TRACE_PTR(%g4, %g6)
78 GET_TRACE_TICK(%g6, %g3)
79 stxa %g6, [%g4 + TRAP_ENT_TICK]%asi
80 rdpr %tl, %g6
81 stha %g6, [%g4 + TRAP_ENT_TL]%asi
82 rdpr %tt, %g6
83 stha %g6, [%g4 + TRAP_ENT_TT]%asi
85 rdpr %tpc, %g6
86 stna %g6, [%g4 + TRAP_ENT_TPC]%asi
87 rdpr %tstate, %g6
[all …]
H A Dwbuf.s62 ! g5 = mmu trap type, g6 = tag access reg (g5 != T_ALIGNMENT) or
77 mov %g6, %g2 ! arg2 = tagaccess
158 FAULT_WINTRACE(%g5, %g6, %g7, TT_F32_SO1)
159 CPU_ADDR(%g5, %g6)
163 ldn [%g5 + CPU_MPCB], %g6
164 ld [%g6 + MPCB_WBCNT], %g5
166 st %g7, [%g6 + MPCB_WBCNT]
171 add %g6, %g7, %g7
174 ldn [%g6 + MPCB_WBUF], %g5
196 ! g5 = mmu trap type, g6 = tag access reg (g5 != T_ALIGNMENT) or
[all …]
H A Dtrap_table.s1036 ldxa [%g5]ASI_DMMU, %g6 /* g6 = primary ctx */ ;\
1037 and %g6, %g4, %g6 /* &= CTXREG_CTX_MASK */ ;\
1038 cmp %g3, %g6 ;\
1042 ldxa [%g5]ASI_DMMU, %g6 /* g6 = secondary ctx */ ;\
1043 and %g6, %g4, %g6 /* &= CTXREG_CTX_MASK */ ;\
1044 cmp %g3, %g6 ;\
1075 mov MMU_TAG_ACCESS, %g6 /* select tag acc */ ;\
1077 ldxa [%g6]ASI_DMMU, %g2 /* g2 = tag access */ ;\
1082 srax %g2, PREDISM_BASESHIFT, %g6 /* g6 > 0 ISM predicted */ ;\
1083 brgz,pn %g6, sfmmu_udtlb_slowpath_ismpred ;\
[all …]
/titanic_50/usr/src/uts/sun4u/cpu/
H A Dus3_cheetahplus_asm.s192 DO_TL1_CPU_LOGOUT(%g3, %g2, %g4, %g5, %g6, %g3, %g4)
221 GET_CPU_IMPL(%g6)
222 cmp %g6, PANTHER_IMPL
227 mov %g6, %g3
249 CH_DCACHE_FLUSHALL(%g4, %g5, %g6)
272 GET_CPU_IMPL(%g6)
276 cmp %g6, PANTHER_IMPL
279 CH_ICACHE_FLUSHALL(%g4, %g5, %g6, %g3)
294 CPU_INDEX(%g6, %g5)
295 sll %g6, TRAPTR_SIZE_SHIFT, %g6
[all …]
H A Dus3_jalapeno_asm.s427 set CHPR_FECCTL0_LOGOUT, %g6
428 DO_CPU_LOGOUT(%g3, %g2, %g6, %g4, %g5, %g6, %g3, %g4)
442 CHK_JP_ERRATA85_ENABLED(%g6, fast_ecc_err_1);
443 set jp_estar_tl0_data, %g6
444 stx %g2, [%g6 + 0]
445 stx %g3, [%g6 + 8]
446 JP_FORCE_FULL_SPEED(%g2, %g3, %g6, %g7) /* %g2: saved speed */
449 ECACHE_FLUSHALL(%g4, %g5, %g6, %g7)
451 CHK_JP_ERRATA85_ENABLED(%g6, fast_ecc_err_2);
452 JP_RESTORE_SPEED(%g2, %g3, %g6, %g7) /* %g2: saved speed */
[all …]
H A Dus3_cheetah_asm.s121 DO_TL1_CPU_LOGOUT(%g3, %g2, %g4, %g5, %g6, %g3, %g4)
152 ASM_LDX(%g6, ecache_tl1_flushaddr)
153 cmp %g6, -1 ! check if address is valid
156 CH_ECACHE_FLUSHALL(%g4, %g5, %g6)
177 CH_DCACHE_FLUSHALL(%g4, %g5, %g6)
200 CH_ICACHE_FLUSHALL(%g4, %g5, %g6, %g3)
215 CPU_INDEX(%g6, %g5)
216 sll %g6, TRAPTR_SIZE_SHIFT, %g6
218 add %g6, %g5, %g6
219 ld [%g6 + TRAPTR_LIMIT], %g5
[all …]
H A Dus3_common_asm.s317 SFMMU_CPU_CNUM(%g2, %g6, %g3) ! %g6 = sfmmu cnum on this CPU
321 or %g6, %g4, %g6 ! %g6 = pgsz | cnum
327 or %g6, %g2, %g6 /* %g6 = nucleus pgsz | primary pgsz | cnum */
328 stxa %g6, [%g4]ASI_DMMU /* wr new ctxum */
395 SFMMU_CPU_CNUM(%g2, %g5, %g6) ! %g5 = sfmmu cnum on this CPU
404 ldxa [%g4]ASI_DMMU, %g6 /* rd old ctxnum */
405 srlx %g6, CTXREG_NEXT_SHIFT, %g2 /* %g2 = nucleus pgsz */
421 stxa %g6, [%g4]ASI_DMMU /* restore old ctxnum */
1355 set CHPR_FECCTL0_LOGOUT, %g6
1356 DO_CPU_LOGOUT(%g3, %g2, %g6, %g4, %g5, %g6, %g3, %g4)
[all …]
H A Dopl_olympus_asm.s210 SFMMU_CPU_CNUM(%g2, %g6, %g3) ! %g6 = sfmmu cnum on this CPU
214 or %g6, %g4, %g6 ! %g6 = primary pgsz | cnum
220 or %g6, %g2, %g6 ! %g6 = nucleus pgsz | primary pgsz | cnum
221 stxa %g6, [%g4]ASI_DMMU ! wr new ctxum
288 SFMMU_CPU_CNUM(%g2, %g5, %g6) ! %g5 = sfmmu cnum on this CPU
297 ldxa [%g4]ASI_DMMU, %g6 /* rd old ctxnum */
298 srlx %g6, CTXREG_NEXT_SHIFT, %g2 /* %g2 = nucleus pgsz */
314 stxa %g6, [%g4]ASI_DMMU /* restore old ctxnum */
887 mov %g0, %g6 ;\
929 mov %g0, %g6 ;\
[all …]
/titanic_50/usr/src/uts/sfmmu/ml/
H A Dsfmmu_asm.s683 SFMMU_MMUID_GNUM_CNUM(%g2, %g5, %g6, %g4)
685 cmp %g6, INVALID_CONTEXT ! hat cnum == INVALID ??
692 mov %g6, %o1
709 mov %g6, %o1
734 SFMMU_MMUID_GNUM_CNUM(%g2, %g5, %g6, %g4)
736 cmp %g6, INVALID_CONTEXT ! hat cnum == INVALID ??
743 mov %g6, %o1
753 mov %g6, %o1
1728 GET_MMU_BOTH_TAGACC(%g5 /*dtag*/, %g2 /*itag*/, %g6, %g4)
1729 rdpr %tt, %g6
[all …]
H A Dsfmmu_kdi.s123 srlx %g1, %g5, %g6; \
125 sllx %g6, %g5, %g5; \
129 sllx %g3, HTAG_REHASH_SHIFT, %g6; \
130 or %g6, SFMMU_INVALID_SHMERID, %g6; \
131 or %g5, %g6, %g5
170 ldxa [%g4]ASI_MEM, %g6; \
172 cmp %g5, %g6; \
178 ldxa [%g4]ASI_MEM, %g6; \
180 cmp %g6, %g2; \
/titanic_50/usr/src/uts/sun4v/ml/
H A Dtrap_table.s1052 sethi %hi(FLUSH_ADDR), %g6 ;\
1053 flush %g6 ;\
1054 TRACE_PTR(%g3, %g6) ;\
1055 GET_TRACE_TICK(%g6, %g4) ;\
1056 stxa %g6, [%g3 + TRAP_ENT_TICK]%asi ;\
1059 rdpr %tnpc, %g6 ;\
1060 stna %g6, [%g3 + TRAP_ENT_F2]%asi ;\
1063 rdpr %tpc, %g6 ;\
1064 stna %g6, [%g3 + TRAP_ENT_TPC]%asi ;\
1065 TRACE_SAVE_TL_GL_REGS(%g3, %g6) ;\
[all …]
H A Dwbuf.s63 ! g5 = mmu trap type, g6 = tag access reg (g5 != T_ALIGNMENT) or
78 mov %g6, %g2 ! arg2 = tagaccess
160 FAULT_WINTRACE(%g5, %g6, %g7, TT_F32_SO1)
161 CPU_PADDR(%g5, %g6)
166 ldxa [%g5 + CPU_MPCB_PA]%asi, %g6
167 lda [%g6 + MPCB_WBCNT]%asi, %g5
169 sta %g7, [%g6 + MPCB_WBCNT]%asi
174 add %g6, %g7, %g7
177 ldxa [%g6 + MPCB_WBUF_PA]%asi, %g5
199 ! g5 = mmu trap type, g6 = tag access reg (g5 != T_ALIGNMENT) or
[all …]
H A Dmach_xc.s79 TRACE_PTR(%g4, %g6)
80 GET_TRACE_TICK(%g6, %g3)
81 stxa %g6, [%g4 + TRAP_ENT_TICK]%asi
82 rdpr %tl, %g6
83 stha %g6, [%g4 + TRAP_ENT_TL]%asi
84 rdpr %tt, %g6
85 stha %g6, [%g4 + TRAP_ENT_TT]%asi
87 rdpr %tpc, %g6
88 stna %g6, [%g4 + TRAP_ENT_TPC]%asi
89 rdpr %tstate, %g6
[all …]
H A Dmach_interrupt.s71 ! %g6 head ptr
74 ldxa [%g3]ASI_QUEUE, %g6 ! %g6 = head ptr
77 cmp %g6, %g7
474 mov %g6, %g2
519 mov %g2, %g6 ! save head in %g2
525 add %g6, %g4, %g4 ! %g4 = PA of ER in Q
563 add %g6, Q_ENTRY_SIZE, %g6 ! increment q head to next
564 and %g6, %g5, %g6 ! size mask for warp around
565 cmp %g6, %g3 ! head == tail ??
575 stxa %g6, [%g4]ASI_QUEUE ! update head offset
/titanic_50/usr/src/uts/sun4/ml/
H A Dinterrupt.s65 ! %g3, %g5, %g6, %g7 - temps
76 add %g1, INTR_HEAD, %g6 ! %g6 = &cpu->m_cpu.intr_head
77 add %g6, %g5, %g6 ! %g6 = &cpu->m_cpu.intr_head[pil]
78 ldn [%g6], %g2 ! %g2 = cpu->m_cpu.intr_head[pil]
94 stn %g3, [%g6] ! update cpu->m_cpu.intr_head[pil]
95 add %g1, INTR_TAIL, %g6 ! %g6 = &cpu->m_cpu.intr_tail
96 stn %g0, [%g5 + %g6] ! clear cpu->m_cpu.intr_tail[pil]
102 TRACE_PTR(%g5, %g6)
103 TRACE_SAVE_TL_GL_REGS(%g5, %g6)
104 rdpr %tt, %g6
[all …]
/titanic_50/usr/src/uts/sun4u/starcat/ml/
H A Ddrmach_asm.s603 set cpu_impl_dual_pgsz, %g6
604 ld [%g6], %g6
605 brz %g6, 1f
608 sethi %hi(ksfmmup), %g6
609 ldx [%g6 + %lo(ksfmmup)], %g6
610 ldub [%g6 + SFMMU_CEXT], %g6
611 sll %g6, TAGACCEXT_SHIFT, %g6
614 stxa %g6, [%g7]ASI_DMMU
619 sethi %hi(FLUSH_ADDR), %g6
622 flush %g6
[all …]
/titanic_50/usr/src/uts/sun4u/starfire/ml/
H A Didn_asm.s300 CPU_INDEX(%g6, %g5) ! g6 = cpuid
305 sll %g6, IDN_DMV_CPU_SHIFT, %g6 ! g6 = cpuid * 8
307 ld [%g6 + %g3], %g5
323 ld [%g6 + %g3], %g2
329 st %g2, [%g3 + %g6]
343 st %g4, [%g3 + %g6]
/titanic_50/usr/src/stand/lib/sa/sparc/
H A D_setjmp.s115 sub %g7, 2, %g6
117 deccc %g6 ! all windows done?
120 sub %g7, 2, %g6
122 deccc %g6 ! all windows done?
/titanic_50/usr/src/uts/sun4u/sys/
H A Dmachthread.h259 CPU_ADDR(%g5, %g6); \
260 ldn [%g5 + CPU_THREAD], %g6; \
261 mov %g6, THREAD_REG; \
H A Dcheetahasm.h1155 stxa %g6, [%g1 + CH_ERR_TL1_G6]%asi; \
1160 rdpr %tl, %g6; \
1161 sub %g6, 1, %g6; \
1162 wrpr %g6, %tl; \
1163 and %g5, 3, %g6; \
1165 or %g3, %g6, %g3; \
1167 srlx %g5, CH_ERR_G2_TO_TSTATE_SHFT, %g6; \
1168 and %g6, 3, %g6; \
1170 or %g6, %g4, %g4; \
1228 ldxa [%g1 + CH_ERR_TL1_G6]%asi, %g6; \
/titanic_50/usr/src/lib/libm/common/C/
H A D__lgamma.c72 g6 = 5.424138599891070494101986e2, variable
243 p = g0+y*(g1+y*(g2+y*(g3+y*(g4+y*(g5+y*(g6+y*g7)))))); in __k_lgamma()
252 p = g0+y*(g1+y*(g2+y*(g3+y*(g4+y*(g5+y*(g6+y*g7)))))); in __k_lgamma()

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