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/titanic_50/usr/src/uts/i86pc/io/fipe/
H A Dfipe_pm.c102 #pragma align CPU_CACHE_COHERENCE_SIZE(fipe_profiles)
109 } fipe_profiles[FIPE_PM_POLICY_MAX] = { variable
1182 fipe_profile_curr = &fipe_profiles[fipe_pm_policy]; in fipe_init()
1323 fipe_profile_curr = &fipe_profiles[fipe_pm_policy]; in fipe_suspend()
1333 fipe_profile_curr = &fipe_profiles[fipe_pm_policy]; in fipe_resume()
1351 fipe_profile_curr = &fipe_profiles[fipe_pm_policy]; in fipe_set_pmpolicy()