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Searched refs:evtchn_upcall_mask (Results 1 – 8 of 8) sorted by relevance

/titanic_50/usr/src/uts/i86xpv/io/psm/
H A Dxpv_uppc.c765 ASSERT(cpu->cpu_m.mcpu_vcpu_info->evtchn_upcall_mask != 0); in xen_uppc_intr_enter()
827 ASSERT(vci->evtchn_upcall_mask != 0); in xen_uppc_setspl()
H A Dxpv_psm.c534 ASSERT(cpu->cpu_m.mcpu_vcpu_info->evtchn_upcall_mask != 0); in xen_psm_intr_enter()
599 ASSERT(vci->evtchn_upcall_mask != 0); in xen_psm_setspl()
/titanic_50/usr/src/uts/common/xen/public/
H A Dxen.h455 uint8_t evtchn_upcall_mask; member
/titanic_50/usr/src/uts/i86pc/ml/
H A Dmach_offsets.in147 evtchn_upcall_mask VCPU_INFO_EVTCHN_UPCALL_MASK
/titanic_50/usr/src/uts/intel/amd64/ml/
H A Dmach_offsets.in174 evtchn_upcall_mask VCPU_INFO_EVTCHN_UPCALL_MASK
/titanic_50/usr/src/uts/i86xpv/os/
H A Dxen_machdep.c527 if (CPU->cpu_m.mcpu_vcpu_info->evtchn_upcall_mask == 0) { in xen_suspend_domain()
668 vcpu->evtchn_upcall_mask, in xen_debug_handler()
H A Devtchn.c992 ASSERT(CPU->cpu_m.mcpu_vcpu_info->evtchn_upcall_mask != 0); in ec_wait_on_evtchn()
/titanic_50/usr/src/uts/i86pc/os/
H A Dstartup.c2244 ASSERT(CPU->cpu_m.mcpu_vcpu_info->evtchn_upcall_mask == 0); in startup_end()