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Searched refs:domain_dimm_sids (Results 1 – 6 of 6) sorted by relevance

/titanic_50/usr/src/uts/sun4u/os/
H A Dplat_ecc_dimm.c144 ASSERT(domain_dimm_sids[bd].pdsb_valid_bitmap); in plat_populate_sid_cache_one()
159 valid = domain_dimm_sids[bd].pdsb_valid_bitmap >> (i * 8) & in plat_populate_sid_cache_one()
173 domain_dimm_sids[bd].pdsb_dimm_sids[(i * 8) + j], in plat_populate_sid_cache_one()
222 switch (domain_dimm_sids[bd].pdsb_state) { in plat_populate_sid_cache()
229 mutex_enter(&domain_dimm_sids[bd]. in plat_populate_sid_cache()
231 domain_dimm_sids[bd].pdsb_state = in plat_populate_sid_cache()
233 mutex_exit(&domain_dimm_sids[bd]. in plat_populate_sid_cache()
251 domain_dimm_sids[bd].pdsb_state, bd); in plat_populate_sid_cache()
296 mutex_enter(&domain_dimm_sids[bd].pdsb_lock); in plat_store_mem_sids()
299 domain_dimm_sids[bd].pdsb_state = PDSB_STATE_FAILED_TO_STORE; in plat_store_mem_sids()
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H A Dplat_ecc_unum.c1129 mutex_init(&domain_dimm_sids[bd].pdsb_lock, in plat_ecc_init()
/titanic_50/usr/src/uts/sun4u/sys/
H A Dplat_ecc_dimm.h105 extern plat_dimm_sid_board_t domain_dimm_sids[];
/titanic_50/usr/src/uts/sun4u/starcat/os/
H A Dstarcat.c103 plat_dimm_sid_board_t domain_dimm_sids[STARCAT_BDSET_MAX]; variable
/titanic_50/usr/src/uts/sun4u/lw8/os/
H A Dlw8_platmod.c161 plat_dimm_sid_board_t domain_dimm_sids[LW8_MAX_CPU_BDS]; variable
/titanic_50/usr/src/uts/sun4u/serengeti/os/
H A Dserengeti.c153 plat_dimm_sid_board_t domain_dimm_sids[SG_MAX_CPU_BDS]; variable