Home
last modified time | relevance | path

Searched refs:dev (Results 1 – 25 of 1628) sorted by relevance

12345678910>>...66

/titanic_50/usr/src/uts/common/io/fibre-channel/fca/oce/
H A Doce_hw.c40 extern int oce_destroy_q(struct oce_dev *dev, struct oce_mbx *mbx,
44 oce_map_regs(struct oce_dev *dev) in oce_map_regs() argument
49 ASSERT(NULL != dev); in oce_map_regs()
50 ASSERT(NULL != dev->dip); in oce_map_regs()
53 ret = ddi_dev_nregs(dev->dip, &dev->num_bars); in oce_map_regs()
55 oce_log(dev, CE_WARN, MOD_CONFIG, in oce_map_regs()
62 ret = ddi_dev_regsize(dev->dip, OCE_DEV_CFG_BAR, &bar_size); in oce_map_regs()
64 oce_log(dev, CE_WARN, MOD_CONFIG, in oce_map_regs()
70 ret = ddi_regs_map_setup(dev->dip, OCE_DEV_CFG_BAR, &dev->dev_cfg_addr, in oce_map_regs()
71 0, bar_size, &reg_accattr, &dev->dev_cfg_handle); in oce_map_regs()
[all …]
H A Doce_main.c73 static void oce_unconfigure(struct oce_dev *dev);
74 static void oce_init_locks(struct oce_dev *dev);
75 static void oce_destroy_locks(struct oce_dev *dev);
76 static void oce_get_params(struct oce_dev *dev);
77 static int oce_get_prop(struct oce_dev *dev, char *propname, int minval,
193 struct oce_dev *dev = NULL; in oce_attach() local
208 dev = kmem_zalloc(sizeof (struct oce_dev), KM_SLEEP); in oce_attach()
211 dev->dip = dip; in oce_attach()
212 dev->dev_id = ddi_get_instance(dip); in oce_attach()
213 dev->suspended = B_FALSE; in oce_attach()
[all …]
H A Doce_gld.c44 static int oce_set_priv_prop(struct oce_dev *dev, const char *name,
47 static int oce_get_priv_prop(struct oce_dev *dev, const char *name,
54 struct oce_dev *dev = arg; in oce_m_start() local
57 mutex_enter(&dev->dev_lock); in oce_m_start()
59 if (dev->state & STATE_MAC_STARTED) { in oce_m_start()
60 mutex_exit(&dev->dev_lock); in oce_m_start()
64 if (dev->suspended) { in oce_m_start()
65 mutex_exit(&dev->dev_lock); in oce_m_start()
68 ret = oce_start(dev); in oce_m_start()
70 mutex_exit(&dev->dev_lock); in oce_m_start()
[all …]
H A Doce_intr.c42 oce_setup_intr(struct oce_dev *dev) in oce_setup_intr() argument
53 ret = ddi_intr_get_supported_types(dev->dip, &intr_types); in oce_setup_intr()
55 oce_log(dev, CE_WARN, MOD_CONFIG, "%s", in oce_setup_intr()
62 dev->intr_type = DDI_INTR_TYPE_MSIX; in oce_setup_intr()
64 nreqd = dev->rx_rings + 1; in oce_setup_intr()
67 dev->intr_type = DDI_INTR_TYPE_FIXED; in oce_setup_intr()
72 ret = ddi_intr_get_nintrs(dev->dip, dev->intr_type, &nsupported); in oce_setup_intr()
74 oce_log(dev, CE_WARN, MOD_CONFIG, in oce_setup_intr()
80 ret = ddi_intr_get_navail(dev->dip, dev->intr_type, &navail); in oce_setup_intr()
82 oce_log(dev, CE_WARN, MOD_CONFIG, in oce_setup_intr()
[all …]
H A Doce_queue.c36 oce_mq_create(struct oce_dev *dev, struct oce_eq *eq, uint32_t q_len);
40 oce_eq_create(struct oce_dev *dev, uint32_t q_len, uint32_t item_size,
45 oce_cq_create(struct oce_dev *dev, struct oce_eq *eq, uint32_t q_len,
51 static struct oce_wq *oce_wq_init(struct oce_dev *dev, uint32_t q_len,
53 static void oce_wq_fini(struct oce_dev *dev, struct oce_wq *wq);
55 static void oce_wq_del(struct oce_dev *dev, struct oce_wq *wq);
57 static struct oce_rq *oce_rq_init(struct oce_dev *dev, uint32_t q_len,
60 static void oce_rq_fini(struct oce_dev *dev, struct oce_rq *rq);
62 static void oce_rq_del(struct oce_dev *dev, struct oce_rq *rq);
73 oce_eq_create(struct oce_dev *dev, uint32_t q_len, uint32_t item_size, in oce_eq_create() argument
[all …]
H A Doce_fm.c43 oce_fm_init(struct oce_dev *dev) in oce_fm_init() argument
47 if (dev->fm_caps == DDI_FM_NOT_CAPABLE) { in oce_fm_init()
51 oce_set_dma_fma_flags(dev->fm_caps); in oce_fm_init()
52 oce_set_reg_fma_flags(dev->fm_caps); in oce_fm_init()
54 (void) ddi_fm_init(dev->dip, &dev->fm_caps, &ibc); in oce_fm_init()
55 if (DDI_FM_EREPORT_CAP(dev->fm_caps) || in oce_fm_init()
56 DDI_FM_ERRCB_CAP(dev->fm_caps)) { in oce_fm_init()
57 pci_ereport_setup(dev->dip); in oce_fm_init()
59 if (DDI_FM_ERRCB_CAP(dev->fm_caps)) { in oce_fm_init()
60 ddi_fm_handler_register(dev->dip, oce_fm_error_cb, in oce_fm_init()
[all …]
/titanic_50/usr/src/uts/common/io/audio/drv/audiosolo/
H A Daudiosolo.c139 struct solo_dev *dev; member
177 struct solo_dev *dev; member
238 solo_dspready(solo_dev_t *dev) in solo_dspready() argument
240 return ((PORT_RD8(dev->sb, 0xc) & 0x80) == 0 ? true : false); in solo_dspready()
244 solo_dspwr(solo_dev_t *dev, uint8_t val) in solo_dspwr() argument
249 if (solo_dspready(dev)) { in solo_dspwr()
250 PORT_WR8(dev->sb, 0xc, val); in solo_dspwr()
256 audio_dev_warn(dev->adev, "solo_dspwr(0x%02x) timed out", val); in solo_dspwr()
261 solo_cmd(solo_dev_t *dev, uint8_t val) in solo_cmd() argument
263 return (solo_dspwr(dev, val)); in solo_cmd()
[all …]
/titanic_50/usr/src/grub/grub-0.97/netboot/
H A Dconfig.c14 static int pci_probe(struct dev *dev, const char *type_name) in pci_probe() argument
26 struct pci_probe_state *state = &dev->state.pci; in pci_probe()
28 if (dev->how_probe == PROBE_FIRST) { in pci_probe()
30 state->dev.driver = 0; in pci_probe()
31 state->dev.bus = 0; in pci_probe()
32 state->dev.devfn = 0; in pci_probe()
33 dev->index = -1; in pci_probe()
36 if ((dev->how_probe != PROBE_AWAKE) && state->advance) { in pci_probe()
37 find_pci(dev->type, &state->dev); in pci_probe()
38 dev->index = -1; in pci_probe()
[all …]
/titanic_50/usr/src/uts/common/io/drm/
H A Ddrm_drv.c169 drm_firstopen(drm_device_t *dev) in drm_firstopen() argument
176 retval = drm_addmap(dev, 0, SAREA_MAX, _DRM_SHM, in drm_firstopen()
183 if (dev->driver->use_agp) { in drm_firstopen()
184 DRM_DEBUG("drm_firstopen: use_agp=%d", dev->driver->use_agp); in drm_firstopen()
185 if (drm_device_is_agp(dev)) in drm_firstopen()
186 dev->agp = drm_agp_init(dev); in drm_firstopen()
187 if (dev->driver->require_agp && dev->agp == NULL) { in drm_firstopen()
193 if (dev->driver->firstopen) in drm_firstopen()
194 retval = dev->driver->firstopen(dev); in drm_firstopen()
201 dev->buf_use = 0; in drm_firstopen()
[all …]
H A Ddrm_irq.c51 if ((irq.busnum >> 8) != dev->pci_domain || in drm_irq_by_busid()
52 (irq.busnum & 0xff) != dev->pci_bus || in drm_irq_by_busid()
53 irq.devnum != dev->pci_slot || in drm_irq_by_busid()
54 irq.funcnum != dev->pci_func) in drm_irq_by_busid()
57 irq.irq = dev->irq; in drm_irq_by_busid()
71 drm_device_t *dev = (void *)arg; in drm_irq_handler_wrap() local
74 mutex_enter(&dev->irq_lock); in drm_irq_handler_wrap()
75 ret = dev->driver->irq_handler(arg); in drm_irq_handler_wrap()
76 mutex_exit(&dev->irq_lock); in drm_irq_handler_wrap()
83 struct drm_device *dev = (struct drm_device *)arg; in vblank_disable_fn() local
[all …]
H A Ddrm_context.c67 drm_ctxbitmap_free(drm_device_t *dev, int ctx_handle) in drm_ctxbitmap_free() argument
70 dev->ctx_bitmap == NULL) { in drm_ctxbitmap_free()
78 clear_bit(ctx_handle, dev->ctx_bitmap); in drm_ctxbitmap_free()
79 dev->context_sareas[ctx_handle] = NULL; in drm_ctxbitmap_free()
85 drm_ctxbitmap_next(drm_device_t *dev) in drm_ctxbitmap_next() argument
89 if (dev->ctx_bitmap == NULL) in drm_ctxbitmap_next()
93 bit = find_first_zero_bit(dev->ctx_bitmap, DRM_MAX_CTXBITMAP); in drm_ctxbitmap_next()
99 set_bit(bit, dev->ctx_bitmap); in drm_ctxbitmap_next()
101 if ((bit+1) > dev->max_context) { in drm_ctxbitmap_next()
102 dev->max_context = (bit+1); in drm_ctxbitmap_next()
[all …]
H A Ddrm_agpsupport.c62 drm_device_is_agp(drm_device_t *dev) in drm_device_is_agp() argument
66 if (dev->driver->device_is_agp != NULL) { in drm_device_is_agp()
73 ret = (*dev->driver->device_is_agp)(dev); in drm_device_is_agp()
78 return (drm_supp_device_capability(dev->drm_handle, PCIY_AGP)); in drm_device_is_agp()
84 drm_device_is_pcie(drm_device_t *dev) in drm_device_is_pcie() argument
86 return (drm_supp_device_capability(dev->drm_handle, PCIY_EXPRESS)); in drm_device_is_pcie()
98 if (!dev->agp || !dev->agp->acquired) in drm_agp_info()
101 agpinfo = &dev->agp->agp_info; in drm_agp_info()
123 if (!dev->agp) { in drm_agp_acquire()
127 ret = ldi_ioctl(dev->agp->agpgart_lh, AGPIOC_ACQUIRE, in drm_agp_acquire()
[all …]
/titanic_50/usr/src/uts/common/io/audio/drv/audioens/
H A Daudioens.c101 struct audioens_dev *dev; member
154 #define GET8(dev, offset) \ argument
155 ddi_get8(dev->acch, (uint8_t *)(dev->regs + (offset)))
156 #define GET16(dev, offset) \ argument
157 ddi_get16(dev->acch, (uint16_t *)(void *)(dev->regs + (offset)))
158 #define GET32(dev, offset) \ argument
159 ddi_get32(dev->acch, (uint32_t *)(void *)(dev->regs + (offset)))
160 #define PUT8(dev, offset, v) \ argument
161 ddi_put8(dev->acch, (uint8_t *)(dev->regs + (offset)), v)
162 #define PUT16(dev, offset, v) \ argument
[all …]
/titanic_50/usr/src/uts/common/io/audio/drv/audiols/
H A Daudiols.c95 static void audigyls_configure_mixer(audigyls_dev_t *dev);
149 read_chan(audigyls_dev_t *dev, int reg, int chn) in read_chan() argument
153 mutex_enter(&dev->low_mutex); in read_chan()
155 OUTL(dev, PR, (reg << 16) | (chn & 0xffff)); in read_chan()
157 val = INL(dev, DR); in read_chan()
158 mutex_exit(&dev->low_mutex); in read_chan()
164 write_chan(audigyls_dev_t *dev, int reg, int chn, uint32_t value) in write_chan() argument
166 mutex_enter(&dev->low_mutex); in write_chan()
168 OUTL(dev, PR, (reg << 16) | (chn & 0x7)); in write_chan()
170 OUTL(dev, DR, value); in write_chan()
[all …]
/titanic_50/usr/src/uts/common/io/audio/drv/audiopci/
H A Daudiopci.c94 struct audiopci_dev *dev; member
115 struct audiopci_dev *dev; member
180 #define GET8(dev, offset) \ argument
181 ddi_get8(dev->acch, (uint8_t *)(dev->regs + (offset)))
182 #define GET16(dev, offset) \ argument
183 ddi_get16(dev->acch, (uint16_t *)(void *)(dev->regs + (offset)))
184 #define GET32(dev, offset) \ argument
185 ddi_get32(dev->acch, (uint32_t *)(void *)(dev->regs + (offset)))
186 #define PUT8(dev, offset, v) \ argument
187 ddi_put8(dev->acch, (uint8_t *)(dev->regs + (offset)), v)
[all …]
/titanic_50/usr/src/uts/common/io/yge/
H A Dyge.c277 yge_dev_t *dev = port->p_dev; in yge_mii_readreg() local
281 GMAC_WRITE_2(dev, pnum, GM_SMI_CTRL, in yge_mii_readreg()
286 val = GMAC_READ_2(dev, pnum, GM_SMI_CTRL); in yge_mii_readreg()
288 val = GMAC_READ_2(dev, pnum, GM_SMI_DATA); in yge_mii_readreg()
306 yge_dev_t *dev = port->p_dev; in yge_mii_writereg() local
309 GMAC_WRITE_2(dev, pnum, GM_SMI_DATA, val); in yge_mii_writereg()
310 GMAC_WRITE_2(dev, pnum, GM_SMI_CTRL, in yge_mii_writereg()
315 if ((GMAC_READ_2(dev, pnum, GM_SMI_CTRL) & GM_SMI_CT_BUSY) == 0) in yge_mii_writereg()
352 yge_dev_t *dev = port->p_dev; in yge_mii_notify() local
363 DEV_LOCK(dev); in yge_mii_notify()
[all …]
/titanic_50/usr/src/uts/common/io/audio/drv/audiocmi/
H A Daudiocmi.c96 cmpci_dev_t *dev = port->dev; in cmpci_open() local
100 mutex_enter(&dev->mutex); in cmpci_open()
106 mutex_exit(&dev->mutex); in cmpci_open()
121 cmpci_dev_t *dev = port->dev; in cmpci_start() local
123 mutex_enter(&dev->mutex); in cmpci_start()
128 SET32(dev, REG_FUNCTRL0, port->fc0_rst_bit); in cmpci_start()
130 CLR32(dev, REG_FUNCTRL0, port->fc0_rst_bit); in cmpci_start()
134 SET32(dev, REG_FUNCTRL1, port->fc1_rate_mask); in cmpci_start()
135 SET32(dev, REG_CHFORMAT, port->chformat_mask); in cmpci_start()
137 if ((port->num == 1) && (dev->maxch > 2)) { in cmpci_start()
[all …]
/titanic_50/usr/src/uts/common/io/audio/drv/audiop16x/
H A Daudiop16x.c132 read_reg(p16x_dev_t *dev, int reg, int chn) in read_reg() argument
136 mutex_enter(&dev->mutex); in read_reg()
137 OUTL(dev, (reg << 16) | (chn & 0xffff), PTR); /* Pointer */ in read_reg()
138 val = INL(dev, DR); /* Data */ in read_reg()
139 mutex_exit(&dev->mutex); in read_reg()
145 write_reg(p16x_dev_t *dev, int reg, int chn, unsigned int value) in write_reg() argument
148 mutex_enter(&dev->mutex); in write_reg()
149 OUTL(dev, (reg << 16) | (chn & 0xffff), PTR); /* Pointer */ in write_reg()
150 OUTL(dev, value, DR); /* Data */ in write_reg()
151 mutex_exit(&dev->mutex); in write_reg()
[all …]
/titanic_50/usr/src/uts/common/xen/io/
H A Dxenbus_probe.c105 free_otherend_details(struct xenbus_device *dev) in free_otherend_details() argument
107 if (dev->otherend != NULL) { in free_otherend_details()
108 kmem_free((void *)dev->otherend, strlen(dev->otherend) + 1); in free_otherend_details()
109 dev->otherend = NULL; in free_otherend_details()
115 free_otherend_watch(struct xenbus_device *dev) in free_otherend_watch() argument
117 if (dev->otherend_watch.node) { in free_otherend_watch()
118 unregister_xenbus_watch(&dev->otherend_watch); in free_otherend_watch()
119 kmem_free((void *)dev->otherend_watch.node, in free_otherend_watch()
120 strlen(dev->otherend_watch.node) + 1); in free_otherend_watch()
121 dev->otherend_watch.node = NULL; in free_otherend_watch()
[all …]
/titanic_50/usr/src/uts/common/avs/ns/nsctl/
H A Dnsc_resv.c148 nsc_dev_t *dev = fd->sf_dev; local
158 mutex_enter(&dev->nsc_lock);
169 mutex_exit(&dev->nsc_lock);
269 nsc_dev_t *dev; in nsc_waiting() local
274 dev = fd->sf_dev; in nsc_waiting()
276 return (dev->nsc_wait || dev->nsc_refcnt <= 0); in nsc_waiting()
301 nsc_dev_t *dev = fd->sf_dev; local
306 if (dev->nsc_wait || dev->nsc_refcnt <= 0)
307 cv_broadcast(&dev->nsc_cv);
309 return (dev->nsc_drop > 0);
[all …]
/titanic_50/usr/src/uts/intel/io/drm/
H A Di915_dma.c50 int i915_wait_ring(drm_device_t * dev, int n, const char *caller) in i915_wait_ring() argument
52 drm_i915_private_t *dev_priv = dev->dev_private; in i915_wait_ring()
55 u32 acthd_reg = IS_I965G(dev) ? ACTHD_I965 : ACTHD; in i915_wait_ring()
83 int i915_init_hardware_status(drm_device_t *dev) in i915_init_hardware_status() argument
85 drm_i915_private_t *dev_priv = dev->dev_private; in i915_init_hardware_status()
89 dmah = drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff,1); in i915_init_hardware_status()
109 void i915_free_hardware_status(drm_device_t *dev) in i915_free_hardware_status() argument
111 drm_i915_private_t *dev_priv = dev->dev_private; in i915_free_hardware_status()
112 if (!I915_NEED_GFX_HWS(dev)) { in i915_free_hardware_status()
115 drm_pci_free(dev, dev_priv->status_page_dmah); in i915_free_hardware_status()
[all …]
H A Dradeon_irq.c74 drm_device_t *dev = (drm_device_t *)(uintptr_t)arg; in radeon_driver_irq_handler() local
76 (drm_radeon_private_t *)dev->dev_private; in radeon_driver_irq_handler()
103 atomic_inc(&dev->vbl_received); in radeon_driver_irq_handler()
105 atomic_inc(&dev->vbl_received2); in radeon_driver_irq_handler()
110 atomic_inc(&dev->vbl_received); in radeon_driver_irq_handler()
112 DRM_WAKEUP(&dev->vbl_queue); in radeon_driver_irq_handler()
113 drm_vbl_send_signals(dev); in radeon_driver_irq_handler()
119 static int radeon_emit_irq(drm_device_t *dev) in radeon_emit_irq() argument
121 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_emit_irq()
137 static int radeon_wait_irq(drm_device_t *dev, int swi_nr) in radeon_wait_irq() argument
[all …]
H A Di915_drv.h217 struct drm_device *dev; member
453 extern void i915_save_display(struct drm_device *dev);
454 extern void i915_restore_display(struct drm_device *dev);
457 extern void i915_kernel_lost_context(drm_device_t * dev);
459 extern int i915_driver_unload(struct drm_device *dev);
460 extern int i915_driver_open(drm_device_t * dev, drm_file_t *file_priv);
461 extern void i915_driver_lastclose(drm_device_t * dev);
462 extern void i915_driver_preclose(drm_device_t * dev, drm_file_t *filp);
463 extern void i915_driver_postclose(drm_device_t * dev,
465 extern int i915_driver_device_is_agp(drm_device_t * dev);
[all …]
/titanic_50/usr/src/cmd/login/
H A Dlogindevperm.sh61 /dev/vt/console_user 0600 /dev/mouse:/dev/kbd
62 /dev/vt/console_user 0600 /dev/sound/* # audio devices
63 /dev/vt/console_user 0600 /dev/fbs/* # frame buffers
64 /dev/vt/console_user 0600 /dev/dri/* # dri devices
65 /dev/vt/console_user 0400 /dev/removable-media/dsk/* # removable media
66 /dev/vt/console_user 0400 /dev/removable-media/rdsk/* # removable media
67 /dev/vt/console_user 0400 /dev/hotpluggable/dsk/* # hotpluggable storage
68 /dev/vt/console_user 0400 /dev/hotpluggable/rdsk/* # hotpluggable storage
69 /dev/vt/console_user 0600 /dev/video[0-9]+ # video devices
70 /dev/vt/console_user 0600 /dev/usb/hid[0-9]+ # hid devices should have the same permission with con…
[all …]
/titanic_50/usr/src/uts/common/sys/fibre-channel/fca/oce/
H A Doce_impl.h161 #define OCE_CSR_READ32(dev, offset) \ argument
162 OCE_READ_REG32((dev)->csr_handle, \
163 (uint32_t *)(void *)((dev)->csr_addr + offset))
165 #define OCE_CSR_WRITE32(dev, offset, value) \ argument
166 OCE_WRITE_REG32((dev)->csr_handle, \
167 (uint32_t *)(void *)((dev)->csr_addr + offset), value)
169 #define OCE_DB_READ32(dev, offset) \ argument
170 OCE_READ_REG32((dev)->db_handle, \
171 (uint32_t *)(void *)((dev)->db_addr + offset))
173 #define OCE_DB_WRITE32(dev, offset, value) \ argument
[all …]

12345678910>>...66