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Searched refs:cycles (Results 1 – 23 of 23) sorted by relevance

/titanic_50/usr/src/cmd/sgs/libelf/misc/
H A Dargs.c147 int cycles,pos; local
148 cycles = c[1] - '0'; pos = c[2] - '1';
149 here.pos += cycles - 1;
151 if(cycles <= 1 || cycles > 9 || pos < 0 || pos >= tmp.pos-1) {
155 while(cycles--) {
/titanic_50/usr/src/uts/sun4v/io/n2rng/
H A Dn2rng_entp_setup.c145 int cycles[LOGIC_TEST_WORDS] = in n2rng_logic_test() local
180 cycles[j] = i; in n2rng_logic_test()
200 i, buffer[i], cycles[i]); in n2rng_logic_test()
208 i, buffer[i], cycles[i]); in n2rng_logic_test()
/titanic_50/usr/src/uts/sun4u/io/
H A Dpanther_asm.s241 ! now delay 15 cycles so we don't have hazard when we return
298 ! now delay 15 cycles so we don't have hazard when we return
494 ! now delay 15 cycles so we don't have hazard when we return
549 ! now delay 15 cycles so we don't have hazard when we return
/titanic_50/usr/src/uts/common/sys/1394/adapters/
H A Dhci1394_ohci.h61 #define OHCI_BUS_CYCLE_TO_uS(cycles) (cycles * OHCI_uS_PER_BUS_CYCLE) argument
62 #define OHCI_BUS_CYCLE_TO_nS(cycles) (cycles * OHCI_nS_PER_BUS_CYCLE) argument
/titanic_50/usr/src/lib/libsqlite/src/
H A Dvdbe.h47 long long cycles; /* Total time spend executing this instruction */ member
H A Dvdbeaux.c652 p->aOp[i].cycles = 0; in sqliteVdbeMakeReady()
906 p->aOp[i].cycles, in sqliteVdbeReset()
907 p->aOp[i].cnt>0 ? p->aOp[i].cycles/p->aOp[i].cnt : 0 in sqliteVdbeReset()
H A Dvdbe.c4788 pOp->cycles += elapse; in sqliteVdbeExec()
/titanic_50/usr/src/uts/common/io/arn/
H A Darn_ani.c712 static uint32_t cycles, rx_clear, rx_frame, tx_frame; in ath9k_hw_GetMibCycleCountsPct() local
720 if (cycles == 0 || cycles > cc) { in ath9k_hw_GetMibCycleCountsPct()
726 uint32_t cc_d = cc - cycles; in ath9k_hw_GetMibCycleCountsPct()
740 cycles = cc; in ath9k_hw_GetMibCycleCountsPct()
/titanic_50/usr/src/uts/common/io/kb8042/
H A Dkb8042.c863 int cycles; local
975 cycles = tmp & 0xffff;
978 if (cycles == 0)
980 else if (cycles == UINT16_MAX)
983 frequency = (PIT_HZ + cycles / 2) / cycles;
/titanic_50/usr/src/man/man9p/
H A DMakefile23 no-involuntary-power-cycles.9p \
/titanic_50/usr/src/uts/common/io/usb/clients/usbkbm/
H A Dusbkbm.c699 int cycles; in usbkbm_ioctl() local
880 cycles = tmp & 0xffff; in usbkbm_ioctl()
883 if (cycles == 0) in usbkbm_ioctl()
885 else if (cycles == UINT16_MAX) in usbkbm_ioctl()
888 frequency = (PIT_HZ + cycles / 2) / cycles; in usbkbm_ioctl()
/titanic_50/usr/src/uts/common/xen/public/
H A Dtrace.h172 } cycles; member
/titanic_50/usr/src/uts/common/xen/dtrace/
H A Dxdt.c721 data = rec->u.cycles.extra_u32; in xdt_process_rec()
722 tsc = (((uint64_t)rec->u.cycles.cycles_hi) << 32) in xdt_process_rec()
723 | rec->u.cycles.cycles_lo; in xdt_process_rec()
1770 stamp = (((uint64_t)rec->u.cycles.cycles_hi) << 32) in xdt_get_first_rec()
1771 | rec->u.cycles.cycles_lo; in xdt_get_first_rec()
/titanic_50/usr/src/pkg/manifests/
H A Dsystem-kernel.man9p.inc19 file path=usr/share/man/man9p/no-involuntary-power-cycles.9p
/titanic_50/usr/src/lib/libc/capabilities/sun4u-us3/common/
H A Dmemcmp.s131 fsrc1 %d8, %d8 ! be used for 3 cycles else we
/titanic_50/usr/src/uts/common/io/
H A Dkbd.c521 int cycles; in kbdioctl() local
576 cycles = tmp & 0xffff; in kbdioctl()
579 if (cycles == 0) in kbdioctl()
581 else if (cycles == UINT16_MAX) in kbdioctl()
584 frequency = (PIT_HZ + cycles / 2) / cycles; in kbdioctl()
/titanic_50/usr/src/lib/libc/capabilities/sun4u/common/
H A Dmemcmp.s127 fsrc1 %d8, %d8 ! be used for 3 cycles else we
/titanic_50/usr/src/uts/common/io/cxgbe/common/
H A Dcommon.h374 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
375 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
H A Dt4_hw.c3398 t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]) in t4_pmtx_get_stats() argument
3405 cycles[i] = t4_read_reg64(adap, A_PM_TX_STAT_LSB); in t4_pmtx_get_stats()
3418 t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]) in t4_pmrx_get_stats() argument
3425 cycles[i] = t4_read_reg64(adap, A_PM_RX_STAT_LSB); in t4_pmrx_get_stats()
/titanic_50/usr/src/uts/common/avs/ns/sdbc/
H A Ddynmem_readme.txt139 at sleeptime2 for 8 cycles even if the number available cache entries
142 for at least 8 cycles even if it floats above pcntfree2 or even pcntfree1.
/titanic_50/usr/src/uts/common/io/sata/impl/
H A Dsata.c9222 uint32_t max_count, cycles; in sata_build_lsense_page_0e() local
9244 cycles = value - worst; in sata_build_lsense_page_0e()
9282 (cycles >> (8 * (3 - i))) & 0xff; in sata_build_lsense_page_0e()
/titanic_50/usr/src/cmd/sgs/packages/common/
H A DSUNWonld-README1033 6299525 .init order failure when processing cycles
/titanic_50/usr/src/uts/intel/io/acpica/
H A Dchanges.txt15236 (1000 cycles of 10us) to try to address AE_TIME errors during EC