Home
last modified time | relevance | path

Searched refs:csr_base (Results 1 – 6 of 6) sorted by relevance

/titanic_50/usr/src/uts/sun4u/io/px/
H A Dpx_hlib.c291 hvio_ib_init(caddr_t csr_base, pxu_t *pxu_p) in hvio_ib_init() argument
297 CSR_XR(csr_base, IMU_ERROR_LOG_ENABLE)); in hvio_ib_init()
300 CSR_XR(csr_base, IMU_INTERRUPT_ENABLE)); in hvio_ib_init()
303 CSR_XR(csr_base, IMU_INTERRUPT_STATUS)); in hvio_ib_init()
306 CSR_XR(csr_base, IMU_ERROR_STATUS_CLEAR)); in hvio_ib_init()
314 ilu_init(caddr_t csr_base, pxu_t *pxu_p) in ilu_init() argument
320 CSR_XR(csr_base, ILU_ERROR_LOG_ENABLE)); in ilu_init()
323 CSR_XR(csr_base, ILU_INTERRUPT_ENABLE)); in ilu_init()
326 CSR_XR(csr_base, ILU_INTERRUPT_STATUS)); in ilu_init()
329 CSR_XR(csr_base, ILU_ERROR_STATUS_CLEAR)); in ilu_init()
[all …]
H A Dpx_err.c733 px_err_reg_enable(px_err_id_t reg_id, caddr_t csr_base) in px_err_reg_enable() argument
741 CSR_XS(csr_base, reg_desc_p->log_addr, log_mask); in px_err_reg_enable()
752 CSR_XS(csr_base, reg_desc_p->enable_addr, 0); in px_err_reg_enable()
753 CSR_XS(csr_base, reg_desc_p->clear_addr, -1); in px_err_reg_enable()
754 CSR_XS(csr_base, reg_desc_p->enable_addr, intr_mask); in px_err_reg_enable()
756 CSR_XR(csr_base, reg_desc_p->enable_addr)); in px_err_reg_enable()
758 CSR_XR(csr_base, reg_desc_p->status_addr)); in px_err_reg_enable()
760 CSR_XR(csr_base, reg_desc_p->clear_addr)); in px_err_reg_enable()
763 CSR_XR(csr_base, reg_desc_p->log_addr)); in px_err_reg_enable()
768 px_err_reg_disable(px_err_id_t reg_id, caddr_t csr_base) in px_err_reg_disable() argument
[all …]
H A Dpx_err_impl.h97 (dev_info_t *rpdip, caddr_t csr_base, ddi_fm_error_t *derr, \
105 (dev_info_t *rpdip, caddr_t csr_base, uint64_t ss_reg, \
119 int px_err_hw_reset_handle(dev_info_t *rpdip, caddr_t csr_base,
122 int px_err_panic_handle(dev_info_t *rpdip, caddr_t csr_base,
125 int px_err_protected_handle(dev_info_t *rpdip, caddr_t csr_base,
128 int px_err_no_panic_handle(dev_info_t *rpdip, caddr_t csr_base,
131 int px_err_no_error_handle(dev_info_t *rpdip, caddr_t csr_base,
156 int px_err_jbc_merge_handle(dev_info_t *rpdip, caddr_t csr_base,
159 int px_err_jbc_jbusint_in_handle(dev_info_t *rpdip, caddr_t csr_base,
162 int px_err_jbc_dmcint_odcd_handle(dev_info_t *rpdip, caddr_t csr_base,
[all …]
H A Dpx_err.h55 void px_err_reg_enable(px_err_id_t reg_id, caddr_t csr_base);
56 void px_err_reg_disable(px_err_id_t reg_id, caddr_t csr_base);
57 void px_err_reg_setup_pcie(uint8_t chip_mask, caddr_t csr_base,
H A Dpx_lib4u.c182 caddr_t xbc_csr_base, csr_base; in px_lib_dev_init() local
218 csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR]; in px_lib_dev_init()
242 hvio_ib_init(csr_base, pxu_p); in px_lib_dev_init()
243 hvio_pec_init(csr_base, pxu_p); in px_lib_dev_init()
244 hvio_mmu_init(csr_base, pxu_p); in px_lib_dev_init()
259 if (CSR_BR(csr_base, ILU_ERROR_LOG_ENABLE, SPARE3)) in px_lib_dev_init()
266 px_err_reg_setup_pcie(chip_mask, csr_base, PX_ERR_ENABLE); in px_lib_dev_init()
270 px_err_reg_setup_pcie(chip_mask, csr_base, PX_ERR_ENABLE); in px_lib_dev_init()
280 *dev_hdl = (devhandle_t)csr_base; in px_lib_dev_init()
293 caddr_t csr_base; in px_lib_dev_fini() local
[all …]
H A Dpx_lib4u.h301 extern void hvio_ib_init(caddr_t csr_base, pxu_t *pxu_p);
302 extern void hvio_mmu_init(caddr_t csr_base, pxu_t *pxu_p);
303 extern void hvio_pec_init(caddr_t csr_base, pxu_t *pxu_p);
394 extern int px_send_pme_turnoff(caddr_t csr_base);
395 extern int px_link_wait4l1idle(caddr_t csr_base);
396 extern int px_link_retrain(caddr_t csr_base);
397 extern void px_enable_detect_quiet(caddr_t csr_base);