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Searched refs:cpu_id (Results 1 – 25 of 273) sorted by relevance

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/titanic_50/usr/src/uts/common/os/
H A Dsoftint.c233 if (CPU_IN_SET(*softcall_cpuset, cp->cpu_id) || in softcall_choose_cpu()
245 if (vcpu_on_pcpu(cp->cpu_id) == VCPU_NOT_ON_PCPU) in softcall_choose_cpu()
251 cpuid = cp->cpu_id; in softcall_choose_cpu()
256 cpuid = cp->cpu_id; in softcall_choose_cpu()
274 CPUSET_ADD(poke, cp->cpu_id); in softcall_choose_cpu()
423 int cpu_id = CPU->cpu_id; in softint() local
432 CPU_IN_SET(*softcall_cpuset, cpu_id)) { in softint()
433 CPUSET_DEL(*softcall_cpuset, cpu_id); in softint()
449 CPU_IN_SET(*softcall_cpuset, cpu_id)) in softint()
450 CPUSET_DEL(*softcall_cpuset, cpu_id); in softint()
[all …]
/titanic_50/usr/src/uts/sun4u/starfire/os/
H A Dbbus_intr.c142 processorid_t cpu_id = CPU->cpu_id; in bbus_intr() local
147 ASSERT(cpu_sgnblkp[cpu_id] != NULL); in bbus_intr()
152 retflag = cpu_sgnblkp[cpu_id]->sigb_host_mbox.flag; in bbus_intr()
188 cmd = cpu_sgnblkp[cpu_id]->sigb_host_mbox.cmd; in bbus_intr()
195 cpu_sgnblkp[cpu_id]->sigb_host_mbox.flag = SIGB_MBOX_BUSY; in bbus_intr()
208 cpu_sgnblkp[cpu_id]->sigb_host_mbox.flag = SIGB_MBOX_EMPTY; in bbus_intr()
279 cpu_sgnblkp[cpu_id]->sigb_host_mbox.cmd = resp; in bbus_intr()
281 (caddr_t)&cpu_sgnblkp[cpu_id]->sigb_host_mbox.data[0], in bbus_intr()
283 cpu_sgnblkp[cpu_id]->sigb_host_mbox.flag = retflag; in bbus_intr()
289 cpu_sgnblkp[cpu_id]->sigb_host_mbox.flag = SIGB_MBOX_EMPTY; in bbus_intr()
[all …]
/titanic_50/usr/src/psm/stand/cpr/sparcv9/sun4u/
H A Dmachdep.c158 restore_tlb(struct sun4u_tlb *utp, int cpu_id) in restore_tlb() argument
181 cpu_id, tname, utp->index, utp->va_tag, in restore_tlb()
206 cb_park_err(int cpu_id) in cb_park_err() argument
208 prom_printf("\ncpu_id %d did not stop!...\n", cpu_id); in cb_park_err()
233 slave_init(int cpu_id) in slave_init() argument
235 restore_tlb(mdinfo.dtte, cpu_id); in slave_init()
236 restore_tlb(mdinfo.itte, cpu_id); in slave_init()
237 CPUSET_ADD(slave_set, cpu_id); in slave_init()
245 cb_park_err(cpu_id); in slave_init()
287 if (scip->node == 0 || scip->cpu_id == cb_mid) in cb_mpsetup()
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/titanic_50/usr/src/cmd/hal/hald/solaris/
H A Ddevinfo_cpu.c51 static int cpu_id = -1; in devinfo_cpu_add() local
95 cpu_id = *int_cpu_id; in devinfo_cpu_add()
102 ++cpu_id; in devinfo_cpu_add()
118 cpu_id = *int_cpu_id; in devinfo_cpu_add()
125 ++cpu_id; in devinfo_cpu_add()
132 HAL_DEBUG (("CPUID=> %x", cpu_id)); in devinfo_cpu_add()
153 devfs_path, cpu_id); in devinfo_cpu_add()
158 HAL_DEBUG(("DevfsPath=> %s, CPUID=> %d", cpu_devfs_path, cpu_id)); in devinfo_cpu_add()
161 "/org/freedesktop/Hal/devices%s_%d", cpu_devfs_path, cpu_id); in devinfo_cpu_add()
179 hal_device_property_set_int (d, "processor.number", cpu_id); in devinfo_cpu_add()
[all …]
/titanic_50/usr/src/uts/sun4/os/
H A Dmp_states.c73 kern_idle[CPU->cpu_id] = 1; in cpu_idle_self()
74 while (kern_idle[CPU->cpu_id]) in cpu_idle_self()
95 cpuid = CPU->cpu_id; in idle_other_cpus()
137 int cpuid = CPU->cpu_id; in resume_other_cpus()
217 int cpuid = cp->cpu_id; in mp_cpu_quiesce()
221 ASSERT(CPU->cpu_id != cpuid); in mp_cpu_quiesce()
270 CPU_SIGNATURE(OS_SIG, SIGST_RUN, SIGSUBST_NULL, cp->cpu_id); in mp_cpu_start()
272 cmp_error_resteer(cp->cpu_id); in mp_cpu_start()
286 cmp_error_resteer(cp->cpu_id); in mp_cpu_stop()
292 CPU_SIGNATURE(OS_SIG, SIGST_OFFLINE, SIGSUBST_NULL, cp->cpu_id); in mp_cpu_stop()
H A Dintr.c222 if (siron_cpu_inum && siron_cpu_inum[CPU->cpu_id] != 0) in siron()
223 inum = siron_cpu_inum[CPU->cpu_id]; in siron()
260 (void) siron_cpu_setup(CPU_CONFIG, c->cpu_id, NULL); in siron_mp_init()
285 int cpuid = CPU->cpu_id; in siron_poke_cpu()
311 siron_cpu_inum[cp->cpu_id] = add_softintr(PIL_1, in siron_cpu_setup()
315 (void) rem_softintr(siron_cpu_inum[cp->cpu_id]); in siron_cpu_setup()
316 siron_cpu_inum[cp->cpu_id] = 0; in siron_cpu_setup()
351 processorid_t cpu_id; in intr_dequeue_req() local
357 cpu_id = CPU->cpu_id; in intr_dequeue_req()
368 next = IV_GET_PIL_NEXT(next, cpu_id); in intr_dequeue_req()
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/titanic_50/usr/src/cmd/dtrace/demo/sched/
H A Dqtime.d28 ts[args[0]->pr_lwpid, args[1]->pr_pid, args[2]->cpu_id] =
33 /ts[args[0]->pr_lwpid, args[1]->pr_pid, args[2]->cpu_id]/
35 @[args[2]->cpu_id] = quantize(timestamp -
36 ts[args[0]->pr_lwpid, args[1]->pr_pid, args[2]->cpu_id]);
37 ts[args[0]->pr_lwpid, args[1]->pr_pid, args[2]->cpu_id] = 0;
H A Dqlen.d29 this->len = qlen[args[2]->cpu_id]++;
30 @[args[2]->cpu_id] = lquantize(this->len, 0, 100);
34 /qlen[args[2]->cpu_id]/
36 qlen[args[2]->cpu_id]--;
H A Dwhosteal.d30 /args[2]->cpu_id != -1 && cpu != args[2]->cpu_id &&
33 @[stringof(args[1]->pr_fname), args[2]->cpu_id] =
H A Dwhoqueue.d36 this->len = ++qlen[this->cpu = args[2]->cpu_id];
70 this->in <= longtime[this->cpu = args[2]->cpu_id]/
79 /qlen[args[2]->cpu_id]/
82 this->len = --qlen[args[2]->cpu_id];
/titanic_50/usr/src/uts/sun4u/io/pci/
H A Dpci_cb.c95 uint32_t cpu_id; in cb_enable_nintr() local
102 cpu_id = intr_dist_cpuid(); in cb_enable_nintr()
105 cpu_id = pc_translate_tgtid(cb_p->cb_ittrans_cookie, cpu_id, in cb_enable_nintr()
109 reg = ib_get_map_reg(mondo, cpu_id); in cb_enable_nintr()
120 pci_p->pci_id, ino, cpu_id); in cb_enable_nintr()
196 uint32_t cpu_id; in cb_intr_dist() local
208 cpu_id = intr_dist_cpuid(); in cb_intr_dist()
210 cpu_id = pc_translate_tgtid(cb_p->cb_ittrans_cookie, cpu_id, in cb_intr_dist()
213 if (ib_map_reg_get_cpu(imr) == cpu_id) in cb_intr_dist()
217 stdphysio(mr_pa, ib_get_map_reg(mondo, cpu_id)); in cb_intr_dist()
H A Dpci_ib.c152 uint_t cpu_id; in ib_intr_enable() local
158 cpu_id = intr_dist_cpuid(); in ib_intr_enable()
160 cpu_id = pc_translate_tgtid(IB2CB(ib_p)->cb_ittrans_cookie, cpu_id, in ib_intr_enable()
164 "ib_intr_enable: ino=%x cpu_id=%x\n", ino, cpu_id); in ib_intr_enable()
166 *imr_p = ib_get_map_reg(mondo, cpu_id); in ib_intr_enable()
227 uint32_t cpu_id; in ib_intr_dist_nintr() local
232 cpu_id = intr_dist_cpuid(); in ib_intr_dist_nintr()
236 cpu_id = pc_translate_tgtid(IB2CB(ib_p)->cb_ittrans_cookie, in ib_intr_dist_nintr()
237 cpu_id, IB_GET_MAPREG_INO(ino)); in ib_intr_dist_nintr()
240 if (ib_map_reg_get_cpu(*imr_p) == cpu_id) in ib_intr_dist_nintr()
[all …]
/titanic_50/usr/src/uts/sun4v/os/
H A Dintrq.c44 "failed, error %lu", cpu->cpu_id, ret); in cpu_intrq_register()
49 "failed, error %lu", cpu->cpu_id, ret); in cpu_intrq_register()
54 "failed, error %lu", cpu->cpu_id, ret); in cpu_intrq_register()
59 "configuration failed, error %lu", cpu->cpu_id, ret); in cpu_intrq_register()
82 cpu->cpu_id); in cpu_intrq_setup()
110 cpu->cpu_id); in cpu_intrq_setup()
124 cpu->cpu_id); in cpu_intrq_setup()
139 cpu->cpu_id); in cpu_intrq_setup()
154 cpu->cpu_id); in cpu_intrq_setup()
171 cpu->cpu_id); in cpu_intrq_setup()
/titanic_50/usr/src/uts/sun4/sys/
H A Divintr.h105 #define IV_GET_PIL_NEXT(iv_p, cpu_id) \ argument
106 (((iv_p->iv_flags & IV_SOFTINT_MT) && (cpu_id != 0)) ? \
107 ((intr_vecx_t *)iv_p)->iv_pil_xnext[cpu_id - 1] : iv_p->iv_pil_next)
108 #define IV_SET_PIL_NEXT(iv_p, cpu_id, next) \ argument
109 (((iv_p->iv_flags & IV_SOFTINT_MT) && (cpu_id != 0)) ? \
110 (((intr_vecx_t *)iv_p)->iv_pil_xnext[cpu_id - 1] = next) : \
/titanic_50/usr/src/lib/libdtrace/common/
H A Dsched.d32 processorid_t cpu_id; /* CPU identifier */ member
42 cpu_id = C->cpu_id;
50 cpu_id = D->disp_cpu == NULL ? -1 :
51 xlate <cpuinfo_t> (D->disp_cpu).cpu_id;
67 inline processorid_t cpu = curcpu->cpu_id;
/titanic_50/usr/src/uts/sun4u/opl/io/pcicmu/
H A Dpcmu_cb.c101 uint32_t cpu_id; in pcmu_cb_enable_nintr() local
110 cpu_id = intr_dist_cpuid(); in pcmu_cb_enable_nintr()
112 cpu_id = u2u_translate_tgtid(pib_p->pib_pcmu_p, cpu_id, imr_p); in pcmu_cb_enable_nintr()
114 reg = ib_get_map_reg(mondo, cpu_id); in pcmu_cb_enable_nintr()
125 pcmu_p->pcmu_id, ino, cpu_id); in pcmu_cb_enable_nintr()
220 uint32_t cpu_id; in pcmu_cb_intr_dist() local
234 cpu_id = intr_dist_cpuid(); in pcmu_cb_intr_dist()
237 cpu_id = u2u_translate_tgtid(pib_p->pib_pcmu_p, cpu_id, imr_p); in pcmu_cb_intr_dist()
240 stdphysio(mr_pa, ib_get_map_reg(mondo, cpu_id)); in pcmu_cb_intr_dist()
H A Dpcmu_intr.c178 uint32_t cpu_id; in pcmu_add_intr() local
212 cpu_id = ino_p->pino_cpuid; in pcmu_add_intr()
213 intr_dist_cpuid_add_device_weight(cpu_id, rdip, 0); in pcmu_add_intr()
246 cpu_id = pcmu_intr_dist_cpuid(pib_p, ino_p); in pcmu_add_intr()
247 ino_p->pino_cpuid = cpu_id; in pcmu_add_intr()
249 intr_dist_cpuid_add_device_weight(cpu_id, rdip, 0); in pcmu_add_intr()
251 cpu_id = u2u_translate_tgtid(pib_p->pib_pcmu_p, in pcmu_add_intr()
252 cpu_id, ino_p->pino_map_reg); in pcmu_add_intr()
253 *ino_p->pino_map_reg = ib_get_map_reg(mondo, cpu_id); in pcmu_add_intr()
H A Dpcmu_ib.c127 uint_t cpu_id; in pcmu_ib_intr_enable() local
133 cpu_id = intr_dist_cpuid(); in pcmu_ib_intr_enable()
134 cpu_id = u2u_translate_tgtid(pcmu_p, cpu_id, imr_p); in pcmu_ib_intr_enable()
136 "pcmu_ib_intr_enable: ino=%x cpu_id=%x\n", ino, cpu_id); in pcmu_ib_intr_enable()
138 *imr_p = ib_get_map_reg(mondo, cpu_id); in pcmu_ib_intr_enable()
216 uint32_t cpu_id; in pcmu_ib_intr_dist_nintr() local
221 cpu_id = intr_dist_cpuid(); in pcmu_ib_intr_dist_nintr()
224 cpu_id = u2u_translate_tgtid(pib_p->pib_pcmu_p, cpu_id, imr_p); in pcmu_ib_intr_dist_nintr()
227 if (ib_map_reg_get_cpu(*imr_p) == cpu_id) { in pcmu_ib_intr_dist_nintr()
230 *imr_p = ib_get_map_reg(PCMU_IB_IMR2MONDO(imr), cpu_id); in pcmu_ib_intr_dist_nintr()
[all …]
/titanic_50/usr/src/uts/i86xpv/os/
H A Dmp_xen.c150 if (cpu == CPU->cpu_id) in vcpu_on_pcpu()
320 return (xen_vcpu_initialize(cp->cpu_id, vgc)); in mp_set_cpu_context()
349 &HYPERVISOR_shared_info->vcpu_info[cp->cpu_id]; in mach_cpucontext_alloc()
514 cpu_phase[CPU->cpu_id] = CPU_PHASE_SAFE; in enter_safe_phase()
515 while (cpu_phase[CPU->cpu_id] == CPU_PHASE_SAFE) in enter_safe_phase()
535 if (cpu_phase[CPU->cpu_id] == CPU_PHASE_WAIT_SAFE) in mach_cpu_idle()
551 if (cpu_phase[CPU->cpu_id] == CPU_PHASE_WAIT_SAFE) in mach_cpu_pause()
562 (void) xen_vcpu_down(CPU->cpu_id); in mach_cpu_halt()
674 ASSERT(CPU->cpu_id != cp->cpu_id); in poweroff_vcpu()
679 if ((error = xen_vcpu_down(cp->cpu_id)) == 0) { in poweroff_vcpu()
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/titanic_50/usr/src/uts/sun4u/os/
H A Dcmp.c148 impl = cpunodes[cp->cpu_id].implementation; in pg_plat_hw_shared()
173 impl = cpunodes[cpu_a->cpu_id].implementation; in pg_plat_cpus_share()
197 impl = cpunodes[cpu->cpu_id].implementation; in pg_plat_hw_instance_id()
208 return ((id_t)((uint_t)cpu->cpu_id & ~(0x1))); in pg_plat_hw_instance_id()
210 return (cpu->cpu_id); in pg_plat_hw_instance_id()
213 return (cmp_cpu_to_chip(cpu->cpu_id)); in pg_plat_hw_instance_id()
219 return (cpu->cpu_id); in pg_plat_hw_instance_id()
/titanic_50/usr/src/uts/i86pc/os/cpupm/
H A Dcpupm_throttle.c211 if (CPU_IN_SET(set, CPU->cpu_id)) { in cpupm_throttle()
213 CPUSET_DEL(set, CPU->cpu_id); in cpupm_throttle()
290 cpupm_throttle_get_max(processorid_t cpu_id) in cpupm_throttle_get_max() argument
292 cpu_t *cp = cpu[cpu_id]; in cpupm_throttle_get_max()
315 "_TPC out of range %d", cp->cpu_id, throtl_level); in cpupm_throttle_get_max()
329 processorid_t cpu_id = cp->cpu_id; in cpupm_throttle_manage_notification() local
358 new_level = cpupm_throttle_get_max(cpu_id); in cpupm_throttle_manage_notification()
/titanic_50/usr/src/uts/i86pc/os/
H A Dmp_startup.c255 set_usegd(&cp->cpu_gdt[GDT_CPUID], SDP_SHORT, NULL, cp->cpu_id, in init_cpu_id_gdt()
258 set_usegd(&cp->cpu_gdt[GDT_CPUID], NULL, cp->cpu_id, SDT_MEMRODA, in init_cpu_id_gdt()
351 cp->cpu_id = cpun; in mp_cpu_configure_common()
498 cpu_del_unit(cp->cpu_id); in mp_cpu_unconfigure_common()
535 trap_trace_ctl_t *ttc = &trap_trace_ctl[cp->cpu_id]; in mp_cpu_unconfigure_common()
682 cp->cpu_id, erratum); in workaround_warning()
700 cp->cpu_id, rw, msr, error); in msr_warning()
1363 cpuid = cp->cpu_id; in mp_start_cpu_common()
1367 "cpu%d: failed to allocate context", cp->cpu_id); in mp_start_cpu_common()
1373 "cpu%d: failed to start, error %d", cp->cpu_id, error); in mp_start_cpu_common()
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H A Dmemscrub.c429 int cpu_id; in system_is_idle() local
435 for (cpu_id = 0; cpu_id < NCPU; ++cpu_id) { in system_is_idle()
436 if (!cpu[cpu_id]) in system_is_idle()
441 if (cpu[cpu_id]->cpu_thread != cpu[cpu_id]->cpu_idle_thread) { in system_is_idle()
442 if (CPU->cpu_id == cpu_id && in system_is_idle()
/titanic_50/usr/src/uts/sun4/io/px/
H A Dpx_ib.c45 uint32_t cpu_id);
114 px_ib_intr_enable(px_t *px_p, cpuid_t cpu_id, devino_t ino) in px_ib_intr_enable() argument
125 "px_ib_intr_enable: ino=%x cpu_id=%x\n", ino, cpu_id); in px_ib_intr_enable()
136 PX_INTR_ENABLE(px_p->px_dip, sysino, cpu_id); in px_ib_intr_enable()
208 px_ib_intr_dist_en(dev_info_t *dip, cpuid_t cpu_id, devino_t ino, in px_ib_intr_dist_en() argument
238 if (cpu_id == old_cpu_id) in px_ib_intr_dist_en()
247 sysino, ino, old_cpu_id, cpu_id); in px_ib_intr_dist_en()
253 PX_INTR_ENABLE(dip, sysino, cpu_id); in px_ib_intr_dist_en()
257 px_ib_cpu_ticks_to_ih_nsec(px_ib_t *ib_p, px_ih_t *ih_p, uint32_t cpu_id) in px_ib_cpu_ticks_to_ih_nsec() argument
277 ih_p->ih_nsec += (uint64_t)tick2ns(ticks, cpu_id); in px_ib_cpu_ticks_to_ih_nsec()
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/titanic_50/usr/src/uts/sun4v/cpu/
H A Dgeneric.c163 cp->cpu_m.cpu_ipipe = cpunodes[cp->cpu_id].exec_unit_mapping; in cpu_map_exec_units()
165 cp->cpu_m.cpu_ipipe = (id_t)(cp->cpu_id); in cpu_map_exec_units()
167 cp->cpu_m.cpu_fpu = cpunodes[cp->cpu_id].fpu_mapping; in cpu_map_exec_units()
169 cp->cpu_m.cpu_fpu = (id_t)(cp->cpu_id); in cpu_map_exec_units()
177 cp->cpu_m.cpu_mpipe = cpunodes[cp->cpu_id].l2_cache_mapping; in cpu_map_exec_units()
181 cp->cpu_m.cpu_core = (id_t)(cp->cpu_id); in cpu_map_exec_units()

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