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Searched refs:cpu_base_spl (Results 1 – 13 of 13) sorted by relevance

/titanic_50/usr/src/uts/i86pc/io/apix/
H A Dapix_intr.c108 if (avp->av_vector != NULL && avp->av_prilevel < cpu->cpu_base_spl) { in apix_remove_pending_av()
236 ASSERT(pil > mcpu->mcpu_pri && pil > cpu->cpu_base_spl); in apix_do_softint_prolog()
356 basespl = cpu->cpu_base_spl; in apix_do_softint_epilog()
398 if (newipl <= oldipl || newipl <= cpu->cpu_base_spl) in apix_do_softint()
420 ASSERT(pil > mcpu->mcpu_pri && pil > cpu->cpu_base_spl); in apix_hilevel_intr_prolog()
586 ASSERT(newipl > LOCK_LEVEL && newipl > cpu->cpu_base_spl); in apix_do_pending_hilevel()
620 ASSERT(pil > mcpu->mcpu_pri && pil > cpu->cpu_base_spl); in apix_intr_thread_prolog()
727 basespl = cpu->cpu_base_spl; in apix_intr_thread_epilog()
762 basespl = cpu->cpu_base_spl; in apix_intr_thread_epilog()
795 if (newipl <= oldipl || newipl <= cpu->cpu_base_spl) in apix_do_pending_hardint()
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H A Dapix.c703 if ((nipl > ipl) && (nipl > cpu->cpu_base_spl)) { in apix_intr_enter()
/titanic_50/usr/src/uts/i86pc/os/
H A Dintr.c513 cpu->cpu_base_spl = active == 0 ? 0 : bsrw_insn(active); in set_base_spl()
816 basespl = cpu->cpu_base_spl; in intr_thread_epilog()
839 basespl = cpu->cpu_base_spl; in intr_thread_epilog()
953 if (pil <= oldpil || pil <= cpu->cpu_base_spl) in dosoftint_prolog()
1094 basespl = cpu->cpu_base_spl; in dosoftint_epilog()
1350 ttp->ttr_spl = cpu->cpu_base_spl; in do_interrupt()
1548 basepri = cpu->cpu_base_spl; in do_splx()
1582 basepri = cpu->cpu_base_spl; in splr()
H A Dcpr_impl.c932 cp->cpu_base_spl)) in i_cpr_start_cpu()
961 PMD(PMD_SX, ("%s() #1 cp->cpu_base_spl %d\n", str, cp->cpu_base_spl)) in i_cpr_start_cpu()
975 cp->cpu_base_spl)) in i_cpr_start_cpu()
985 cp->cpu_base_spl)) in i_cpr_start_cpu()
990 cp->cpu_base_spl)) in i_cpr_start_cpu()
H A Dmp_startup.c368 cp->cpu_base_spl = ipltospl(LOCK_LEVEL); in mp_cpu_configure_common()
1806 ASSERT(cp->cpu_base_spl == ipltospl(LOCK_LEVEL)); in mp_startup_common()
/titanic_50/usr/src/uts/i86pc/ml/
H A Doffsets.in203 cpu_base_spl
/titanic_50/usr/src/uts/common/sys/
H A Dcpuvar.h150 int cpu_base_spl; /* priority for highest rupt active */ member
/titanic_50/usr/src/uts/sun4/ml/
H A Doffsets.in344 cpu_base_spl
H A Dinterrupt.s697 wrpr %g0, DISP_LEVEL, %pil ! up from cpu_base_spl
2229 movl %xcc, %o1, %o2 ! cpu_base_spl.
/titanic_50/usr/src/uts/sun4v/ml/
H A Dmach_locore.s1011 ! set %pil from max(old pil, cpu_base_spl)
/titanic_50/usr/src/uts/sun4u/ml/
H A Dmach_locore.s847 ! set %pil from max(old pil, cpu_base_spl)
/titanic_50/usr/src/uts/i86xpv/os/
H A Devtchn.c1323 ttp->ttr_spl = cpu->cpu_base_spl; in xen_callback_handler()
/titanic_50/usr/src/cmd/mdb/common/modules/genunix/
H A Dgenunix.c2955 bspl = cpu->cpu_base_spl; in cpuinfo_walk_cpu()