Home
last modified time | relevance | path

Searched refs:core_ctl (Results 1 – 2 of 2) sorted by relevance

/titanic_50/usr/src/uts/intel/pcbe/
H A Dcore_pcbe.c184 uint64_t core_ctl; /* Event Select bits */ member
1055 if (conf->core_ctl & n->restricted_bits) { in check_cpc_securitypolicy()
1099 conf.core_ctl = eventcode->eventselect; in configure_gpc()
1100 conf.core_ctl |= eventcode->unitmask << in configure_gpc()
1107 conf.core_ctl = event_num & 0xFF; in configure_gpc()
1118 conf.core_ctl = k->event_num; in configure_gpc()
1119 conf.core_ctl |= k->umask << CORE_UMASK_SHIFT; in configure_gpc()
1180 conf.core_ctl = n->event_num; /* Event Select */ in configure_gpc()
1199 conf.core_ctl &= ~ (CORE_UMASK_MASK << in configure_gpc()
1202 conf.core_ctl |= attrs[i].ka_val << in configure_gpc()
[all …]
/titanic_50/usr/src/uts/common/io/ixgbe/core/
H A Dixgbe_82599.c2051 u32 core_ctl; in ixgbe_read_analog_reg8_82599() local
2059 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL); in ixgbe_read_analog_reg8_82599()
2060 *val = (u8)core_ctl; in ixgbe_read_analog_reg8_82599()
2075 u32 core_ctl; in ixgbe_write_analog_reg8_82599() local
2079 core_ctl = (reg << 8) | val; in ixgbe_write_analog_reg8_82599()
2080 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl); in ixgbe_write_analog_reg8_82599()