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Searched refs:control_2 (Results 1 – 5 of 5) sorted by relevance

/titanic_50/usr/src/uts/common/io/xge/hal/xgehal/
H A Dxgehal-ring-fp.c162 rxdp->control_1 = rxdp->control_2 = 0; in xge_hal_ring_dtr_reserve()
196 ext_info->vlan = XGE_HAL_RXD_GET_VLAN_TAG(rxdp->control_2); in xge_hal_ring_dtr_info_get()
207 ext_info->rth_value = XGE_HAL_RXD_1_GET_RTH_VALUE(rxdp->control_2); in xge_hal_ring_dtr_info_get()
235 ext_info->vlan = XGE_HAL_RXD_GET_VLAN_TAG(rxdp->control_2); in xge_hal_ring_dtr_info_nb_get()
270 rxdp->control_2 &= (~XGE_HAL_RXD_1_MASK_BUFFER0_SIZE); in xge_hal_ring_dtr_1b_set()
271 rxdp->control_2 |= XGE_HAL_RXD_1_SET_BUFFER0_SIZE(size); in xge_hal_ring_dtr_1b_set()
275 rxdp->control_2, in xge_hal_ring_dtr_1b_set()
302 *pkt_length = XGE_HAL_RXD_1_GET_BUFFER0_SIZE(rxdp->control_2); in xge_hal_ring_dtr_1b_get()
332 rxdp->control_2 &= (~XGE_HAL_RXD_3_MASK_BUFFER0_SIZE); in xge_hal_ring_dtr_3b_set()
333 rxdp->control_2 |= XGE_HAL_RXD_3_SET_BUFFER0_SIZE(sizes[0]); in xge_hal_ring_dtr_3b_set()
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H A Dxgehal-fifo-fp.c118 txdp->control_1, txdp->control_2, txdp->buffer_pointer, in __hal_fifo_dtr_post_single()
362 txdp->control_1 = txdp->control_2 = 0; in xge_hal_fifo_dtr_reserve_many()
444 txdp->control_1 = txdp->control_2 = 0; in xge_hal_fifo_dtr_reserve()
514 txdp_first->control_2 |= fifo->interrupt_type; in xge_hal_fifo_dtr_post()
568 txdp_first->control_2 |= fifo->interrupt_type; in xge_hal_fifo_dtr_post_many()
847 txdp->control_1 = txdp->control_2 = 0; in xge_hal_fifo_dtr_buffer_set_aligned()
897 txdp->control_2 = 0; in xge_hal_fifo_dtr_buffer_set_aligned()
980 txdp->control_1 = txdp->control_2 = 0; in xge_hal_fifo_dtr_buffer_finalize()
1048 txdp->control_1 = txdp->control_2 = 0; in xge_hal_fifo_dtr_buffer_set()
1116 txdp->control_2 |= cksum_bits; in xge_hal_fifo_dtr_cksum_set_bits()
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H A Dxgehal-device.c5657 txdp->control_1, txdp->control_2, txdp->buffer_pointer, in xge_hal_device_handle_tcode()
5697 rxdp->control_2, rxdp->buffer0_ptr, in xge_hal_device_handle_tcode()
/titanic_50/usr/src/uts/common/io/xge/hal/include/
H A Dxgehal-ring.h55 #define XGE_HAL_RXD_SET_VLAN_TAG(control_2, val) control_2 |= (u16)val argument
56 #define XGE_HAL_RXD_GET_VLAN_TAG(control_2) ((u16)(control_2 & 0xFFFF)) argument
126 u64 control_2; member
143 u64 control_2; member
188 u64 control_2; member
H A Dxgehal-fifo.h109 u64 control_2; member