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Searched refs:chips (Results 1 – 12 of 12) sorted by relevance

/titanic_50/usr/src/uts/sun4u/os/
H A Dcmp.c45 static cpuset_t chips[MAX_CPU_CHIPID]; variable
57 return (!CPUSET_ISNULL(chips[chipid])); in cmp_cpu_is_cmp()
67 CPUSET_ADD(chips[chipid], cpuid); in cmp_add_cpu()
80 CPUSET_DEL(chips[chipid], cpuid); in cmp_delete_cpu()
104 mycores = chips[chipid]; in cmp_error_resteer()
134 ASSERT(cpuid < MAX_CPU_CHIPID && CPUSET_ISNULL(chips[cpuid])); in cmp_cpu_to_chip()
/titanic_50/usr/src/uts/intel/ia32/os/
H A Dcpc_subr.c246 group_t *chips; in kcpc_hw_lwp_hook() local
257 chips = pghw_set_lookup(PGHW_CHIP); in kcpc_hw_lwp_hook()
258 if (chips == NULL) { in kcpc_hw_lwp_hook()
264 while ((chip = group_iterate(chips, &i)) != NULL) { in kcpc_hw_lwp_hook()
/titanic_50/usr/src/uts/sun4u/io/
H A Dopl_cfg.c186 hwd_cpu_chip_t *chips; in opl_dump_hwd() local
227 chips = &sbp->sb_cmu.cmu_cpu_chips[0]; in opl_dump_hwd()
230 status = chips[i].chip_status; in opl_dump_hwd()
954 hwd_cpu_chip_t *chips; in opl_probe_cpu_chips() local
958 chips = &probe->pr_sb->sb_cmu.cmu_cpu_chips[0]; in opl_probe_cpu_chips()
964 if (!HWD_STATUS_OK(chips[i].chip_status)) in opl_probe_cpu_chips()
/titanic_50/usr/src/cmd/fm/dicts/
H A DSCF.po1253 msgstr "An uncorrectable error was detected on a DMA channel between two MBC chips on two\ndifferen…
1255 msgstr "There are two DMA channels between MBC chips. If the first DMA channel fails, the system\nw…
1257 …BC chip that has failed, the XSCF will no longer be able \nto contact the chips and devices that a…
1303 msgstr "Resources associated with this SC chip (this includes CPU chips, memory, and I/O) will be d…
1305 msgstr "No immediate action. Resources associated with this SC chip (this includes CPU chips, memor…
1813 msgstr "A fatal error on the interface between two SC chips has occurred.\n Refer to %s for more i…
1815 msgstr "Some number of CPU chips, some number of MAC chips, and some amount of IO will be deconfigu…
1831 msgstr "Some number of CPU chips, some number of MAC chips, and some amount of IO will be deconfigu…
1925 msgstr "The number of correctable errors on the interface between two SC chips has exceeded an acce…
1927 msgstr "Some resources associated with the SC chips (CPU chips, memory, IO Channels) will be deconf…
[all …]
H A DSUN4V.po855 msgstr "The system's capacity to correct transmission errors between CPU chips has been reduced.\n"
1347 msgstr "A CRC error has occurred in the interconnect between two CPU chips.\nWhile no data has been…
1351 msgstr "The system's capacity to correct transmission errors between CPU chips\nhas been reduced.\n"
/titanic_50/usr/src/cmd/fm/eversholt/files/i386/i86pc/
H A Dgcpu.esc142 * whether or not current chips have dcaches at all levels.
H A Dintel.esc130 * whether or not current chips have dcaches at all levels.
/titanic_50/usr/src/cmd/fm/eversholt/files/sparc/sun4v/
H A Dgcpu.esc316 * If ereport does not have a sender, all chips are faulted
381 * If ereport does not have a sender, all chips will be faulted
/titanic_50/usr/src/uts/common/io/e1000api/
H A DREADME614 6756917 LSO is not enabled on some e1000g chips
645 6781905 super slow throughput on e1000g 82541 and 82547 chips
702 6847888 HW initialization updates for 82541 and 82547 chips
/titanic_50/usr/src/uts/common/io/e1000g/
H A DREADME614 6756917 LSO is not enabled on some e1000g chips
645 6781905 super slow throughput on e1000g 82541 and 82547 chips
702 6847888 HW initialization updates for 82541 and 82547 chips
/titanic_50/usr/src/uts/common/sys/scsi/adapters/
H A Dscr.ss26 ; Symbios 53C825/875 host bus adapter chips.
/titanic_50/usr/src/data/hwdata/
H A Dpci.ids6344 # Motorola made a mistake and used 1507 instead of 1057 in some chips. Please look at the 1507 entr…
14687 # This device ID was used for earlier chips.
19232 # Should be HTEC Ltd, but there are no known HTEC chips and 1507 is already used by mistake by Moto…
24480 18df 1214 2x 1GbE, PCIe x1, dual Intel 82571EB chips