| /titanic_50/usr/src/uts/i86pc/io/pciex/ |
| H A D | npe_misc.c | 49 void npe_ck804_fix_aer_ptr(ddi_acc_handle_t cfg_hdl);
51 void npe_nvidia_error_workaround(ddi_acc_handle_t cfg_hdl);
52 void npe_intel_error_workaround(ddi_acc_handle_t cfg_hdl);
54 int npe_enable_htmsi(ddi_acc_handle_t cfg_hdl);
116 npe_ck804_fix_aer_ptr(ddi_acc_handle_t cfg_hdl) in npe_ck804_fix_aer_ptr() argument
120 if ((pci_config_get16(cfg_hdl, PCI_CONF_VENID) == NVIDIA_VENDOR_ID) && in npe_ck804_fix_aer_ptr()
121 (pci_config_get16(cfg_hdl, PCI_CONF_DEVID) == in npe_ck804_fix_aer_ptr()
123 (pci_config_get8(cfg_hdl, PCI_CONF_REVID) >= in npe_ck804_fix_aer_ptr()
125 cya1 = pci_config_get16(cfg_hdl, NVIDIA_CK804_VEND_CYA1_OFF); in npe_ck804_fix_aer_ptr()
127 (void) pci_config_put16(cfg_hdl, in npe_ck804_fix_aer_ptr()
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| H A D | npe.c | 179 extern void npe_ck804_fix_aer_ptr(ddi_acc_handle_t cfg_hdl);
181 extern void npe_nvidia_error_workaround(ddi_acc_handle_t cfg_hdl);
182 extern void npe_intel_error_workaround(ddi_acc_handle_t cfg_hdl);
859 ddi_acc_handle_t cfg_hdl; in npe_initchild() local
948 if (pci_config_setup(child, &cfg_hdl) == DDI_SUCCESS) { in npe_initchild()
949 npe_ck804_fix_aer_ptr(cfg_hdl); in npe_initchild()
950 npe_nvidia_error_workaround(cfg_hdl); in npe_initchild()
951 npe_intel_error_workaround(cfg_hdl); in npe_initchild()
952 pci_config_teardown(&cfg_hdl); in npe_initchild()
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| /titanic_50/usr/src/uts/intel/io/pciex/ |
| H A D | pcieb_x86.c | 466 ddi_acc_handle_t cfg_hdl = bus_p->bus_cfg_hdl; in pcieb_intel_serr_workaround() local
497 data = (uint32_t)pci_config_get32(cfg_hdl, in pcieb_intel_serr_workaround()
502 pci_config_put32(cfg_hdl, reg->offset, value); in pcieb_intel_serr_workaround()
503 value = (uint32_t)pci_config_get32(cfg_hdl, in pcieb_intel_serr_workaround()
507 data = (uint32_t)pci_config_get16(cfg_hdl, in pcieb_intel_serr_workaround()
512 pci_config_put16(cfg_hdl, reg->offset, in pcieb_intel_serr_workaround()
514 value = (uint32_t)pci_config_get16(cfg_hdl, in pcieb_intel_serr_workaround()
518 data = (uint32_t)pci_config_get8(cfg_hdl, in pcieb_intel_serr_workaround()
523 pci_config_put8(cfg_hdl, reg->offset, in pcieb_intel_serr_workaround()
525 value = (uint32_t)pci_config_get8(cfg_hdl, in pcieb_intel_serr_workaround()
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| /titanic_50/usr/src/uts/common/io/ |
| H A D | pci_intr_lib.c | 1014 ddi_acc_handle_t cfg_hdl; in pci_intx_get_cap() local
1023 if (pci_config_setup(dip, &cfg_hdl) != DDI_SUCCESS) { in pci_intx_get_cap()
1029 savereg = pci_config_get16(cfg_hdl, PCI_CONF_COMM); in pci_intx_get_cap()
1035 pci_config_put16(cfg_hdl, PCI_CONF_COMM, cmdreg); in pci_intx_get_cap()
1038 statreg = pci_config_get16(cfg_hdl, PCI_CONF_STAT); in pci_intx_get_cap()
1044 cmdreg = pci_config_get16(cfg_hdl, PCI_CONF_COMM); in pci_intx_get_cap()
1058 pci_config_put16(cfg_hdl, PCI_CONF_COMM, savereg); in pci_intx_get_cap()
1060 pci_config_teardown(&cfg_hdl); in pci_intx_get_cap()
1074 ddi_acc_handle_t cfg_hdl; in pci_intx_clr_mask() local
1079 if (pci_config_setup(dip, &cfg_hdl) != DDI_SUCCESS) { in pci_intx_clr_mask()
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| /titanic_50/usr/src/uts/intel/io/pci/ |
| H A D | pci_pci.c | 232 static boolean_t ppb_ht_msimap_check(ddi_acc_handle_t cfg_hdl);
233 static int ppb_ht_msimap_set(ddi_acc_handle_t cfg_hdl, int cmd);
825 ppb_ht_msimap_check(ddi_acc_handle_t cfg_hdl) in ppb_ht_msimap_check() argument
829 if (pci_htcap_locate(cfg_hdl, in ppb_ht_msimap_check()
840 ppb_ht_msimap_set(ddi_acc_handle_t cfg_hdl, int cmd) in ppb_ht_msimap_set() argument
845 if (pci_htcap_locate(cfg_hdl, PCI_HTCAP_TYPE_MASK, in ppb_ht_msimap_set()
849 reg = pci_config_get16(cfg_hdl, ptr + PCI_CAP_ID_REGS_OFF); in ppb_ht_msimap_set()
859 pci_config_put16(cfg_hdl, ptr + PCI_CAP_ID_REGS_OFF, reg); in ppb_ht_msimap_set()
871 ddi_acc_handle_t cfg_hdl; in ppb_intr_ops() local
897 if (pci_config_setup(pdip, &cfg_hdl) != DDI_SUCCESS) { in ppb_intr_ops()
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| /titanic_50/usr/src/uts/common/io/pciex/ |
| H A D | pcieb.c | 294 ddi_acc_handle_t cfg_hdl; in pcieb_41210_mps_wkrnd() local
310 if (sdip == cdip || pci_config_setup(sdip, &cfg_hdl) in pcieb_41210_mps_wkrnd()
315 bus_dev_ven_id = pci_config_get32(cfg_hdl, PCI_CONF_VENID); in pcieb_41210_mps_wkrnd()
317 pci_config_teardown(&cfg_hdl); in pcieb_41210_mps_wkrnd()
321 if (PCI_CAP_LOCATE(cfg_hdl, PCI_CAP_ID_PCI_E, &cap_ptr) in pcieb_41210_mps_wkrnd()
323 pci_config_teardown(&cfg_hdl); in pcieb_41210_mps_wkrnd()
328 sdip_dev_ctrl = PCI_CAP_GET16(cfg_hdl, NULL, cap_ptr, in pcieb_41210_mps_wkrnd()
337 pci_config_teardown(&cfg_hdl); in pcieb_41210_mps_wkrnd()
347 PCI_CAP_PUT16(cfg_hdl, NULL, cap_ptr, PCIE_DEVCTL, in pcieb_41210_mps_wkrnd()
356 pci_config_teardown(&cfg_hdl); in pcieb_41210_mps_wkrnd()
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| H A D | pcie.c | 2377 pcie_check_io_mem_range(ddi_acc_handle_t cfg_hdl, boolean_t *empty_io_range, in pcie_check_io_mem_range() argument
2383 class = pci_config_get8(cfg_hdl, PCI_CONF_BASCLASS); in pcie_check_io_mem_range()
2384 subclass = pci_config_get8(cfg_hdl, PCI_CONF_SUBCLASS); in pcie_check_io_mem_range()
2387 val = (((uint_t)pci_config_get8(cfg_hdl, PCI_BCNF_IO_BASE_LOW) & in pcie_check_io_mem_range()
2395 val = (((uint_t)pci_config_get16(cfg_hdl, PCI_BCNF_MEM_BASE) & in pcie_check_io_mem_range()
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| /titanic_50/usr/src/uts/sun4u/io/pci/ |
| H A D | pci_intr.c | 305 ddi_acc_handle_t cfg_hdl = ih_p->ih_config_handle; in pci_intr_wrapper() local
307 if (pci_intr_dma_sync && cfg_hdl && pbm_p->pbm_sync_reg_pa) { in pci_intr_wrapper()
308 (void) pci_config_get16(cfg_hdl, PCI_CONF_VENID); in pci_intr_wrapper()
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| /titanic_50/usr/src/uts/common/io/myri10ge/drv/ |
| H A D | myri10ge_var.h | 473 ddi_acc_handle_t cfg_hdl; member
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| H A D | myri10ge.c | 4875 ddi_acc_handle_t handle = mgp->cfg_hdl; in myri10ge_reset_nic()
5713 ddi_acc_handle_t handle = mgp->cfg_hdl; in myri10ge_save_pci_state()
5733 ddi_acc_handle_t handle = mgp->cfg_hdl; in myri10ge_restore_pci_state()
5878 mgp->cfg_hdl = handle; in myri10ge_attach()
6088 pci_config_teardown(&mgp->cfg_hdl); in myri10ge_detach()
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