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Searched refs:XG_SERDES_ADDR_RDY (Results 1 – 2 of 2) sorted by relevance

/titanic_50/usr/src/uts/common/io/fibre-channel/fca/qlge/
H A Dqlge_dbg.c1830 XG_SERDES_ADDR_RDY, BIT_SET, 0) != DDI_SUCCESS) in ql_read_serdes_reg()
1836 XG_SERDES_ADDR_RDY, BIT_SET, 0) != DDI_SUCCESS) in ql_read_serdes_reg()
/titanic_50/usr/src/uts/common/sys/fibre-channel/fca/qlge/
H A Dqlge_hw.h1876 #define XG_SERDES_ADDR_RDY BIT_31 macro