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Searched refs:UNDEF_IRO (Results 1 – 4 of 4) sorted by relevance

/titanic_50/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/fw/
H A D57710_int_offsets.h67 {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_HIGIG_HDR_LENGTH_OFFSET(portId)
68 {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_VF_SPQ_PAGE_BASE_OFFSET(vfId)
69 {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_VF_SPQ_PROD_OFFSET(vfId)
70 {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_VF_SPQ_DATA_OFFSET(vfId)
86 {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_TIME_SYNC_TEST_ADDRESS_OFFSET
102 {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_ERROR_HANDLER_STATISTICS_RAM_OFFSET
103 {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_LB_PHYSICAL_QUEUES_INFO_OFFSET
104 {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_QUEUE_ZONE_OFFSET(queueId)
105 {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_VF_ZONE_OFFSET(vfId)
106 {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_FIVE_TUPLE_SRC_EN_OFFSET
[all …]
H A D57711_int_offsets.h67 {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_HIGIG_HDR_LENGTH_OFFSET(portId)
68 {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_VF_SPQ_PAGE_BASE_OFFSET(vfId)
69 {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_VF_SPQ_PROD_OFFSET(vfId)
70 {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_VF_SPQ_DATA_OFFSET(vfId)
86 {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_TIME_SYNC_TEST_ADDRESS_OFFSET
102 {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_ERROR_HANDLER_STATISTICS_RAM_OFFSET
103 {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_LB_PHYSICAL_QUEUES_INFO_OFFSET
104 {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_QUEUE_ZONE_OFFSET(queueId)
105 {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_VF_ZONE_OFFSET(vfId)
106 {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_FIVE_TUPLE_SRC_EN_OFFSET
[all …]
H A D57712_int_offsets.h112 {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_VFC_TEST_LINE_OFFSET
113 {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_VFC_TEST_RESULT_OFFSET
132 {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_KUKU_TIME_SYNC_FLG_OFFSET(funcId)
148 {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_VFC_TEST_RSS_KEY_OFFSET(portId)
154 {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_VFC_TEST_LINE_OFFSET
155 {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_VFC_TEST_RESULT_OFFSET
177 …{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // CSTORM_HC_SYNC_LINE_INDEX_E1X_OFFSET(hcInd…
220 {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(pfId)
239 {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(pfId)
240 {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_MAC_FILTER_CONFIG_OFFSET(pfId)
[all …]
H A Dmicrocode_constants.h87 #define UNDEF_IRO 0x80000000 macro