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Searched refs:UINT64_C (Results 1 – 25 of 27) sorted by relevance

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/titanic_50/usr/src/lib/udapl/libdat/include/dat/
H A Dudat.h283 #define DAT_PROVIDER_FIELD_PROVIDER_NAME UINT64_C(0x0000001)
284 #define DAT_PROVIDER_FIELD_PROVIDER_VERSION_MAJOR UINT64_C(0x0000002)
285 #define DAT_PROVIDER_FIELD_PROVIDER_VERSION_MINOR UINT64_C(0x0000004)
286 #define DAT_PROVIDER_FIELD_DAPL_VERSION_MAJOR UINT64_C(0x0000008)
287 #define DAT_PROVIDER_FIELD_DAPL_VERSION_MINOR UINT64_C(0x0000010)
288 #define DAT_PROVIDER_FIELD_LMR_MEM_TYPE_SUPPORTED UINT64_C(0x0000020)
289 #define DAT_PROVIDER_FIELD_IOV_OWNERSHIP UINT64_C(0x0000040)
290 #define DAT_PROVIDER_FIELD_DAT_QOS_SUPPORTED UINT64_C(0x0000080)
291 #define DAT_PROVIDER_FIELD_COMPLETION_FLAGS_SUPPORTED UINT64_C(0x0000100)
292 #define DAT_PROVIDER_FIELD_IS_THREAD_SAFE UINT64_C(0x0000200)
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H A Ddat.h393 #define DAT_IA_FIELD_IA_ADAPTER_NAME UINT64_C(0x000000001)
394 #define DAT_IA_FIELD_IA_VENDOR_NAME UINT64_C(0x000000002)
395 #define DAT_IA_FIELD_IA_HARDWARE_MAJOR_VERSION UINT64_C(0x000000004)
396 #define DAT_IA_FIELD_IA_HARDWARE_MINOR_VERSION UINT64_C(0x000000008)
397 #define DAT_IA_FIELD_IA_FIRMWARE_MAJOR_VERSION UINT64_C(0x000000010)
398 #define DAT_IA_FIELD_IA_FIRMWARE_MINOR_VERSION UINT64_C(0x000000020)
399 #define DAT_IA_FIELD_IA_ADDRESS_PTR UINT64_C(0x000000040)
400 #define DAT_IA_FIELD_IA_MAX_EPS UINT64_C(0x000000080)
401 #define DAT_IA_FIELD_IA_MAX_DTO_PER_EP UINT64_C(0x000000100)
402 #define DAT_IA_FIELD_IA_MAX_RDMA_READ_PER_EP_IN UINT64_C(0x000000200)
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H A Ddat_platform_specific.h153 #ifndef UINT64_C
154 #define UINT64_C(c) c ## ULL
184 #ifndef UINT64_C
185 #define UINT64_C(c) c ## i64
/titanic_50/usr/src/uts/intel/sys/
H A Dcontrolregs.h192 #define AMD_DC_CFG_DIS_CNV_WC_SSO (UINT64_C(1) << 3)
193 #define AMD_DC_CFG_DIS_SMC_CHK_BUF (UINT64_C(1) << 10)
199 #define AMD_HWCR_TLBCACHEDIS (UINT64_C(1) << 3)
207 #define AMD_NB_CFG_SRQ_HEARTBEAT (UINT64_C(1) << 20)
208 #define AMD_NB_CFG_SRQ_SPR (UINT64_C(1) << 32)
212 #define AMD_BU_CFG_E298 (UINT64_C(1) << 1)
216 #define AMD_DE_CFG_E721 (UINT64_C(1))
229 #define AMD_GH_NB_CFG_EN_ECS (UINT64_C(1) << 46)
/titanic_50/usr/src/grub/grub-0.97/stage2/
H A Dcontrolregs.h135 #define AMD_DC_CFG_DIS_CNV_WC_SSO (UINT64_C(1) << 3)
136 #define AMD_DC_CFG_DIS_SMC_CHK_BUF (UINT64_C(1) << 10)
151 #define AMD_NB_CFG_SRQ_HEARTBEAT (UINT64_C(1) << 20)
152 #define AMD_NB_CFG_SRQ_SPR (UINT64_C(1) << 32)
/titanic_50/usr/src/uts/sparc/v9/sys/
H A Dvis_simulator.h136 #define GSR_ALIGN_MASK UINT64_C(0x0000000000000007)
138 #define GSR_SCALE_MASK UINT64_C(0x00000000000000f8)
140 #define GSR_IRND_MASK UINT64_C(0x0000000006000000)
142 #define GSR_IM_MASK UINT64_C(0x0000000008000000)
144 #define GSR_MASK_MASK UINT64_C(0xffffffff00000000)
/titanic_50/usr/src/uts/sun4/sys/
H A Ddmv.h67 ((UINT64_C(1) << 63) | \
68 ((((uint64_t)(dmv_inum)) & UINT64_C(DMV_INUM_MASK)) << \
70 (((uint64_t)(dev_private)) & UINT64_C(DMV_PRIVATE_MASK)))
/titanic_50/usr/src/uts/sun4u/pcbe/
H A Dopl_pcbe.c167 #define SPARC64_VI_PCR_PRIVPIC UINT64_C(0)
174 #define CPC_SPARC64_VI_PCR_PIC_MASK UINT64_C(0x3F)
180 #define CPC_SPARC64_VI_PCR_SC_MASK UINT64_C(0x7)
182 #define CPC_SPARC64_VI_PCR_NC_MASK UINT64_C(0x7)
185 #define CPC_SPARC64_VI_PCR_OVF_MASK UINT64_C(0xffff)
187 #define SPARC64_VI_PCR_SYS (UINT64_C(1) << CPC_SPARC64_VI_PCR_SYS_SHIFT)
188 #define SPARC64_VI_PCR_USR (UINT64_C(1) << CPC_SPARC64_VI_PCR_USR_SHIFT)
189 #define SPARC64_VI_PCR_ULRO (UINT64_C(1) << CPC_SPARC64_VI_PCR_ULRO_SHIFT)
190 #define SPARC64_VI_PCR_OVRO (UINT64_C(1) << CPC_SPARC64_VI_PCR_OVRO_SHIFT)
217 ((pcr) & (UINT64_C(1) << (CPC_SPARC64_VI_PCR_OVF_SHIFT + picno)))
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H A Dus234_pcbe.c139 #define ULTRA_PCR_SYS (UINT64_C(1) << CPC_ULTRA_PCR_SYS)
140 #define ULTRA_PCR_PRIVPIC (UINT64_C(1) << CPC_ULTRA_PCR_PRIVPIC)
147 #define CPC_ULTRA2_PCR_PIC_MASK UINT64_C(0xf)
148 #define CPC_ULTRA3_PCR_PIC_MASK UINT64_C(0x3f)
/titanic_50/usr/src/uts/sun4v/sys/
H A Dniagara2regs.h80 #define CPC_PCR_PIC0_MASK UINT64_C(0xfff)
81 #define CPC_PCR_PIC1_MASK UINT64_C(0xfff)
85 #define CPC_PCR_OV0_MASK UINT64_C(0x40000)
86 #define CPC_PCR_OV1_MASK UINT64_C(0x80000000)
H A Dniagararegs.h50 #define CPC_PCR_PIC0_MASK UINT64_C(0x7)
51 #define CPC_PCR_PIC1_MASK UINT64_C(0)
53 #define CPC_PCR_OVF_MASK UINT64_C(0x300)
/titanic_50/usr/src/lib/libcpc/common/
H A Dlibcpc_impl.h220 #define CPC_ULTRA2_PCR_PIC0_MASK UINT64_C(0xf)
221 #define CPC_ULTRA3_PCR_PIC0_MASK UINT64_C(0x3f)
223 #define CPC_ULTRA2_PCR_PIC1_MASK UINT64_C(0xf)
224 #define CPC_ULTRA3_PCR_PIC1_MASK UINT64_C(0x3f)
/titanic_50/usr/src/lib/libcpc/sparc/
H A Devent_ultra.c166 UINT64_C(1), CPC_ULTRA_PCR_USR },
168 UINT64_C(1), CPC_ULTRA_PCR_SYS },
177 UINT64_C(1), CPC_ULTRA_PCR_USR },
179 UINT64_C(1), CPC_ULTRA_PCR_SYS },
225 *bits = UINT64_C(1) << CPC_ULTRA_PCR_USR; in cpc_strtoevent()
234 *bits = UINT64_C(1) << CPC_ULTRA_PCR_USR; in cpc_strtoevent()
/titanic_50/usr/src/uts/common/sys/
H A Dint_const.h99 #define UINT64_C(c) __CONCAT__(c,ul) macro
103 #define UINT64_C(c) __CONCAT__(c,ull)
/titanic_50/usr/src/uts/sun4u/sys/
H A Dopl_olympus_regs.h47 #undef UINT64_C
48 #define UINT64_C(x) (x) macro
H A Dcheetahregs.h59 #undef UINT64_C
61 #define UINT64_C(x) (x) macro
888 #define JG_LRU_MASK UINT64_C(0x0000040000000000) /* PA<42> LRU bit */
1137 #define LOGOUT_INVALID UINT64_C(0xecc1ecc1ecc1ecc1)
H A Dstarfire.h150 (UINT64_C(1) << STARFIRE_MC_MEMBOARD_SHIFT)
/titanic_50/usr/src/uts/common/sys/scsi/targets/
H A Dstdef.h1408 #define SP_BLK UINT64_C(0x0000000000000000)
1409 #define SP_FLM UINT64_C(0x2000000000000000)
1410 #define SP_SQFLM UINT64_C(0x4000000000000000)
1411 #define SP_EOD UINT64_C(0x6000000000000000)
1412 #define SP_BACKSP UINT64_C(0x8000000000000000)
1413 #define SP_CMD_MASK UINT64_C(0x6000000000000000)
1414 #define SP_CNT_MASK UINT64_C(0x1fffffffffffffff)
/titanic_50/usr/src/uts/common/os/
H A Dlog_sysevent.c523 SE_ATTR_PTR(ev) = UINT64_C(0); in sysevent_alloc()
670 if (SE_ATTR_PTR(ev) != UINT64_C(0)) { in sysevent_attach_attributes()
696 SE_ATTR_PTR(ev) = UINT64_C(0); in sysevent_detach_attributes()
775 SE_ATTR_PTR(copy) = UINT64_C(0); in se_repack()
1649 eid->eid_seq = UINT64_C(0); in queue_sysevent()
1656 eid->eid_seq = UINT64_C(0); in queue_sysevent()
/titanic_50/usr/src/uts/i86pc/sys/
H A Dmachparam.h144 #define KERNEL_TEXT_amd64 UINT64_C(0xfffffffffb800000)
/titanic_50/usr/src/uts/sun4u/starfire/sys/
H A Didn.h1005 ((((uint64_t)(cookie) & UINT64_C(_IDNPD_COOKIE_MASK)) << \
1007 (((uint64_t)idn.version & UINT64_C(_IDNPD_VER_MASK)) << \
1009 (((uint64_t)(mtype) & UINT64_C(_IDNPD_MTYPE_MASK)) << \
1011 (((uint64_t)(atype) & UINT64_C(_IDNPD_ATYPE_MASK)) << \
1013 (((uint64_t)idn.localid & UINT64_C(_IDNPD_DOMID_MASK)) << \
1015 (((uint64_t)CPU->cpu_id & UINT64_C(_IDNPD_CPUID_MASK)) << \
/titanic_50/usr/src/uts/sun4v/pcbe/
H A Dniagara_pcbe.c136 #define ULTRA_PCR_PRIVPIC (UINT64_C(1) << CPC_PCR_PRIVPIC)
H A Dniagara2_pcbe.c145 #define ULTRA_PCR_PRIVPIC (UINT64_C(1) << CPC_PCR_PRIV_SHIFT)
/titanic_50/usr/src/uts/common/fs/ufs/
H A Dlufs.c51 #define LUFS_GENID_PRIME UINT64_C(4294967291)
52 #define LUFS_GENID_BASE UINT64_C(311)
/titanic_50/usr/src/uts/intel/pcbe/
H A Dp4_pcbe.c145 #define MASK40 UINT64_C(0xffffffffff)

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