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Searched refs:UBC_INTERRUPT_ENABLE (Results 1 – 3 of 3) sorted by relevance

/titanic_50/usr/src/uts/sun4u/io/px/
H A Doberon_regs.h36 #define UBC_INTERRUPT_ENABLE 0x471008 macro
H A Dpx_err.c1267 CSR_XR(csr_base, UBC_INTERRUPT_ENABLE), in PX_ERPT_SEND_DEC()
1285 CSR_XR(csr_base, UBC_INTERRUPT_ENABLE), in PX_ERPT_SEND_DEC()
H A Dpx_hlib.c143 UBC_INTERRUPT_ENABLE
277 CSR_XR(xbc_csr_base, UBC_INTERRUPT_ENABLE)); in ubc_init()