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Searched refs:TX_RING_SIZE (Results 1 – 10 of 10) sorted by relevance

/titanic_50/usr/src/grub/grub-0.97/netboot/
H A Depic100.c17 #define TX_RING_SIZE 2 /* use at least 2 buffers for TX */ macro
87 static struct epic_tx_desc tx_ring[TX_RING_SIZE]
90 static unsigned char tx_packet[PKT_BUF_SZ * TX_RING_SIZE];
282 for (i = 0; i < TX_RING_SIZE; i++) { in epic100_init_ring()
309 entry = cur_tx % TX_RING_SIZE; in epic100_transmit()
H A Dvia-rhine.c416 #define TX_RING_SIZE 2 macro
634 char *tx_buffs[TX_RING_SIZE];
644 struct sk_buff *tx_skbuff[TX_RING_SIZE];
698 for (i = 0; i < TX_RING_SIZE; i++) in rhine_init_ring()
1105 static char desc1[TX_RING_SIZE * sizeof (struct rhine_tx_desc) + 32]; in rhine_reset()
1106 static char desc2[TX_RING_SIZE * sizeof (struct rhine_tx_desc) + 32]; in rhine_reset()
1146 for (i = 0; i < TX_RING_SIZE; i++) in rhine_reset()
1262 entry = tp->cur_tx % TX_RING_SIZE; in rhine_transmit()
H A Dw89c840.c110 #define TX_RING_SIZE 2 macro
232 struct w840_tx_desc tx_ring[TX_RING_SIZE];
262 static char tx_packet[PKT_BUF_SZ * TX_RING_SIZE];
499 entry = w840private.cur_tx % TX_RING_SIZE; in w89c840_transmit()
516 if (entry >= TX_RING_SIZE-1) /* Wrap ring */ in w89c840_transmit()
936 for (i = 0; i < TX_RING_SIZE; i++) { in init_ring()
H A Dpcnet32.c159 #define TX_RING_SIZE (1 << (PCNET32_LOG_TX_BUFFERS)) macro
160 #define TX_RING_MOD_MASK (TX_RING_SIZE - 1)
188 static unsigned char txb[PKT_BUF_SZ * TX_RING_SIZE];
237 static struct pcnet32_tx_head tx_ring[TX_RING_SIZE]
262 struct sk_buff *tx_skbuff[TX_RING_SIZE];
419 for (i = 0; i < TX_RING_SIZE; i++) { in pcnet32_init_ring()
H A Dsundance.c117 #define TX_RING_SIZE 2 macro
254 static struct netdev_desc tx_ring[TX_RING_SIZE];
258 static unsigned char txb[PKT_BUF_SZ * TX_RING_SIZE];
H A Dtulip.c397 #define TX_RING_SIZE 2 macro
398 static struct tulip_tx_desc tx_ring[TX_RING_SIZE] __attribute__ ((aligned(4)));
/titanic_50/usr/src/uts/intel/io/amd8111s/
H A Damd8111s_hw.h101 #define TX_RING_SIZE (1 << (TX_RING_LEN_BITS)) macro
103 #define TX_RING_MOD_MASK (2 * TX_RING_SIZE - 1)
105 #define TX_RESCHEDULE_THRESHOLD (TX_RING_SIZE >> 1)
H A Damd8111s_main.c831 length = sizeof (struct tx_desc) * TX_RING_SIZE + ALIGNMENT; in amd8111s_allocate_descriptors()
865 pMil->pNonphysical->TxDescQEnd = &(pMil->Tx_desc[TX_RING_SIZE -1]); in amd8111s_allocate_descriptors()
873 for (i = 0; i < TX_RING_SIZE; i++) { in amd8111s_allocate_descriptors()
1428 while ((pTx_desc->Tx_OWN == 0) && (desc_count < TX_RING_SIZE)) { in amd8111s_tx_drain()
1433 if (desc_count == TX_RING_SIZE) { in amd8111s_tx_drain()
H A Damd8111s_hw.c705 pMdl->TxRingSize = TX_RING_SIZE; in mdlSetResources()
1712 for (i = 0; i < TX_RING_SIZE; i++) { in milResetTxQ()
1953 TxRingSize = TX_RING_SIZE; in milSetResources()
/titanic_50/usr/src/uts/common/io/sfe/
H A Dsfe.c93 #ifndef TX_RING_SIZE
95 #define TX_RING_SIZE TX_BUF_SIZE macro
97 #define TX_RING_SIZE (TX_BUF_SIZE * 4) macro
2182 gcp->gc_tx_ring_size = TX_RING_SIZE; in sfeattach()