| /titanic_50/usr/src/uts/common/io/hxge/ |
| H A D | hpi_txdma.c | 50 TXDMA_REG_WRITE64(handle, TDC_PAGE_HANDLE, channel, hdl_p->value); in hpi_txdma_log_page_handle_set()
107 TXDMA_REG_WRITE64(handle, TDC_TDR_CFG, channel, cfg.value); in hpi_txdma_channel_control()
114 TXDMA_REG_WRITE64(handle, TDC_TDR_CFG, channel, cfg.value); in hpi_txdma_channel_control()
124 TXDMA_REG_WRITE64(handle, TDC_TDR_CFG, channel, cfg.value); in hpi_txdma_channel_control()
131 TXDMA_REG_WRITE64(handle, TDC_TDR_CFG, channel, cfg.value); in hpi_txdma_channel_control()
138 TXDMA_REG_WRITE64(handle, TDC_TDR_CFG, channel, cfg.value); in hpi_txdma_channel_control()
153 TXDMA_REG_WRITE64(handle, TDC_STAT, channel, cs.value); in hpi_txdma_channel_control()
185 TXDMA_REG_WRITE64(handle, TDC_STAT, channel, cs_p->value); in hpi_txdma_control_status()
190 TXDMA_REG_WRITE64(handle, TDC_STAT, channel, in hpi_txdma_control_status()
223 TXDMA_REG_WRITE64(handle, TDC_INT_MASK, channel, mask_p->value); in hpi_txdma_event_mask()
[all …]
|
| H A D | hpi_txdma.h | 57 #define TXDMA_REG_WRITE64(handle, reg, channel, data) \ macro
|
| H A D | hxge_txdma.c | 175 TXDMA_REG_WRITE64(handle, TDC_TDR_KICK, channel, 0); in hxge_reset_txdma_channel()
2641 TXDMA_REG_WRITE64(hxgep->hpi_handle, TDC_STAT_INT_DBG, channel, 0); in hxge_tx_err_evnts()
2774 TXDMA_REG_WRITE64(handle, TDC_TDR_KICK, channel, 0); in hxge_txdma_fatal_err_recover()
|
| H A D | hxge_send.c | 791 TXDMA_REG_WRITE64(HXGE_DEV_HPI_HANDLE(hxgep), in hxge_start()
|
| /titanic_50/usr/src/uts/common/io/nxge/npi/ |
| H A D | npi_tx_wr64.h | 37 static void TXDMA_REG_WRITE64(npi_handle_t, uint64_t, int, uint64_t);
38 #pragma inline(TXDMA_REG_WRITE64)
122 TXDMA_REG_WRITE64( in TXDMA_REG_WRITE64() function
|
| H A D | npi_txdma.c | 229 TXDMA_REG_WRITE64(handle, tdc_dmc_offset[i], tdc, value); in npi_txdma_tdc_regs_zero()
939 TXDMA_REG_WRITE64(handle, TX_CS_REG, channel, cs.value); in npi_txdma_channel_control()
944 TXDMA_REG_WRITE64(handle, TX_CS_REG, channel, cs.value); in npi_txdma_channel_control()
954 TXDMA_REG_WRITE64(handle, TX_CS_REG, channel, cs.value); in npi_txdma_channel_control()
961 TXDMA_REG_WRITE64(handle, TX_CS_REG, channel, cs.value); in npi_txdma_channel_control()
968 TXDMA_REG_WRITE64(handle, TX_CS_REG, channel, cs.value); in npi_txdma_channel_control()
981 TXDMA_REG_WRITE64(handle, TX_CS_REG, channel, cs.value); in npi_txdma_channel_control()
988 TXDMA_REG_WRITE64(handle, TX_CS_REG, channel, cs.value); in npi_txdma_channel_control()
998 TXDMA_REG_WRITE64(handle, TX_CS_REG, channel, cs.value); in npi_txdma_channel_control()
1057 TXDMA_REG_WRITE64(handle, TX_CS_REG, channel, cs_p->value); in npi_txdma_control_status()
[all …]
|
| /titanic_50/usr/src/uts/common/io/nxge/ |
| H A D | nxge_txdma.c | 288 TXDMA_REG_WRITE64(handle, TX_RING_KICK_REG, channel, 0); in nxge_reset_txdma_channel()
3265 TXDMA_REG_WRITE64(nxgep->npi_handle, TDMC_INTR_DBG_REG, channel, 0); in nxge_tx_err_evnts()
3336 TXDMA_REG_WRITE64(handle, TX_RING_KICK_REG, channel, 0); in nxge_txdma_fatal_err_recover()
3516 TXDMA_REG_WRITE64(handle, TX_RING_KICK_REG, tdc, 0); in nxge_tx_port_fatal_err_recover()
3681 TXDMA_REG_WRITE64(nxgep->npi_handle, TDMC_INTR_DBG_REG, in nxge_txdma_inject_err()
|
| H A D | nxge_send.c | 1016 TXDMA_REG_WRITE64( in nxge_start()
1059 TXDMA_REG_WRITE64(NXGE_DEV_NPI_HANDLE(nxgep), in nxge_start()
|