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Searched refs:SUNI1x10GEXP_REG_MSTAT_CONTROL (Results 1 – 3 of 3) sorted by relevance

/titanic_50/usr/src/uts/common/io/chxge/com/
H A Dmy3126.c99 (void) t1_tpi_write(adapter, OFFSET(SUNI1x10GEXP_REG_MSTAT_CONTROL), in my3126_interrupt_handler()
H A Dpm3393.c381 (void) pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_CONTROL, in pm3393_enable_port()
576 (void) pmwrite(mac, SUNI1x10GEXP_REG_MSTAT_CONTROL, in pm3393_update_statistics()
H A Dsuni1x10gexp_regs.h187 #define SUNI1x10GEXP_REG_MSTAT_CONTROL 0x2100 macro