Searched refs:SB_CSR_DPERR_S0 (Results 1 – 2 of 2) sorted by relevance
140 #define SB_CSR_DPERR_S0 0x0001000000000000ULL /* SBus slot 0 DVMA parity err */ macro
805 SB_CSR_DPERR_S2|SB_CSR_DPERR_S1|SB_CSR_DPERR_S0|SB_CSR_PIO_PERRS)) { in sbus_ctrl_ecc_err()863 if (t_sb_csr & SB_CSR_DPERR_S0) { in sbus_log_csr_error()