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Searched refs:REG_WR_IND (Results 1 – 3 of 3) sorted by relevance

/titanic_50/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/
H A Dlm_hw_init_reset.c1255 REG_WR_IND(pdev,rq_onchip_at_reg+temp*8,0); in uninit_pxp2_blk()
1256 REG_WR_IND(pdev,rq_onchip_at_reg+temp*8+4,on_chip_addr2_val); in uninit_pxp2_blk()
1684 REG_WR_IND( pdev, offset, val_32[0] ); in lm_reset_nig_values_for_func_save_restore()
1685 REG_WR_IND( pdev, offset+4, val_32[1] ); in lm_reset_nig_values_for_func_save_restore()
2800 REG_WR_IND(pdev,rq_onchip_at_reg+temp*8,ONCHIP_ADDR1(addr_table[k][i].as_u64)); in init_pxp2_func()
2801 REG_WR_IND(pdev,rq_onchip_at_reg+temp*8+4,ONCHIP_ADDR2(addr_table[k][i].as_u64)); in init_pxp2_func()
2854 REG_WR_IND(pdev,QM_REG_PTRTBL +8*i ,0); in init_qm_common()
2855 REG_WR_IND(pdev,QM_REG_PTRTBL +8*i +4 ,0); in init_qm_common()
2863 REG_WR_IND(pdev,QM_REG_PTRTBL_EXT_A +8*i ,0); in init_qm_common()
2864 REG_WR_IND(pdev,QM_REG_PTRTBL_EXT_A +8*i +4 ,0); in init_qm_common()
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H A Dlm_power.c173 REG_WR_IND( pdev, reg_be+val, val_32[0] ) ; in init_nwuf_57710()
174 REG_WR_IND( pdev, reg_be+val+4, val_32[1] ) ; in init_nwuf_57710()
/titanic_50/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/include/
H A Dlm5710.h3932 #define REG_WR_IND(_pdev, _reg_offset, _val) lm_reg_wr_ind(_pdev, (_reg_offset), _val) macro