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Searched refs:REG_WRITE (Results 1 – 9 of 9) sorted by relevance

/titanic_50/usr/src/uts/common/io/arn/
H A Darn_hw.c328 REG_WRITE(ah, AR_PHY(0x36), 0x00007058); in ath9k_hw_get_radiorev()
331 REG_WRITE(ah, AR_PHY(0x20), 0x00010000); in ath9k_hw_get_radiorev()
346 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); in ath9k_hw_disablepcie()
347 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); in ath9k_hw_disablepcie()
348 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); in ath9k_hw_disablepcie()
349 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); in ath9k_hw_disablepcie()
350 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); in ath9k_hw_disablepcie()
351 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); in ath9k_hw_disablepcie()
352 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); in ath9k_hw_disablepcie()
353 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); in ath9k_hw_disablepcie()
[all …]
H A Darn_ani.c279 REG_WRITE(ah, AR_PHY_ERR_1, aniState->ofdmPhyErrBase); in ath9k_ani_restart()
280 REG_WRITE(ah, AR_PHY_ERR_2, aniState->cckPhyErrBase); in ath9k_ani_restart()
281 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); in ath9k_ani_restart()
282 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); in ath9k_ani_restart()
564 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); in ath9k_ani_reset()
565 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); in ath9k_ani_reset()
612 REG_WRITE(ah, AR_PHY_ERR_1, in ath9k_hw_ani_monitor()
614 REG_WRITE(ah, AR_PHY_ERR_MASK_1, in ath9k_hw_ani_monitor()
623 REG_WRITE(ah, AR_PHY_ERR_2, in ath9k_hw_ani_monitor()
625 REG_WRITE(ah, AR_PHY_ERR_MASK_2, in ath9k_hw_ani_monitor()
[all …]
H A Darn_mac.c42 REG_WRITE(ah, AR_IMR_S0, in ath9k_hw_set_txq_interrupts()
45 REG_WRITE(ah, AR_IMR_S1, in ath9k_hw_set_txq_interrupts()
60 REG_WRITE(ah, AR_MACMISC, in ath9k_hw_dmaRegDump()
134 REG_WRITE(ah, AR_QTXDP(q), txdp); in ath9k_hw_puttxbuf()
145 REG_WRITE(ah, AR_Q_TXE, 1 << q); in ath9k_hw_txstart()
187 REG_WRITE(ah, AR_TXCFG, in ath9k_hw_updatetxtriglevel()
202 REG_WRITE(ah, AR_Q_TXD, 1 << q); in ath9k_hw_stoptxdma()
217 REG_WRITE(ah, AR_QUIET2, SM(10, AR_QUIET2_QUIET_DUR)); in ath9k_hw_stoptxdma()
218 REG_WRITE(ah, AR_QUIET_PERIOD, 100); in ath9k_hw_stoptxdma()
219 REG_WRITE(ah, AR_NEXT_QUIET_TIMER, tsfLow >> 10); in ath9k_hw_stoptxdma()
[all …]
H A Darn_calib.c221 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ); in ath9k_hw_setup_calibration()
227 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN); in ath9k_hw_setup_calibration()
232 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER); in ath9k_hw_setup_calibration()
237 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT); in ath9k_hw_setup_calibration()
534 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val); in ath9k_hw_adc_gaincal_calibrate()
541 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0), in ath9k_hw_adc_gaincal_calibrate()
594 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val); in ath9k_hw_adc_dccal_calibrate()
600 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0), in ath9k_hw_adc_dccal_calibrate()
694 REG_WRITE(ah, ar5416_cca_regs[i], val); in ath9k_hw_loadnf()
716 REG_WRITE(ah, ar5416_cca_regs[i], val); in ath9k_hw_loadnf()
[all …]
H A Darn_phy.c72 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, in ath9k_hw_set_channel()
75 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, in ath9k_hw_set_channel()
102 REG_WRITE(ah, AR_PHY(0x37), reg32); in ath9k_hw_set_channel()
137 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, in ath9k_hw_ar9280_set_channel()
140 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, in ath9k_hw_ar9280_set_channel()
173 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); in ath9k_hw_ar9280_set_channel()
431 REG_WRITE(ah, AR_PHY_BASE + 0xD8, bank6SelMask); in ath9k_hw_decrease_chain_power()
445 REG_WRITE(ah, AR_PHY_BASE + 0xD8, 0x00000053); in ath9k_hw_decrease_chain_power()
447 REG_WRITE(ah, PHY_SWITCH_CHAIN_0, in ath9k_hw_decrease_chain_power()
H A Darn_eeprom.c69 REG_WRITE(ah, reg, regVal); in ath9k_hw_analog_shift_rmw()
1108 REG_WRITE(ah, in ath9k_hw_set_def_power_cal_table()
1128 REG_WRITE(ah, regOffset, reg32); in ath9k_hw_set_def_power_cal_table()
1225 REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset, in ath9k_hw_set_4k_power_cal_table()
1244 REG_WRITE(ah, regOffset, reg32); in ath9k_hw_set_4k_power_cal_table()
1865 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, in ath9k_hw_def_set_txpower()
1870 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2, in ath9k_hw_def_set_txpower()
1877 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3, in ath9k_hw_def_set_txpower()
1882 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4, in ath9k_hw_def_set_txpower()
1889 REG_WRITE(ah, AR_PHY_POWER_TX_RATE5, in ath9k_hw_def_set_txpower()
[all …]
H A Darn_ath9k.h612 #define REG_WRITE(_ah, _reg, _val) arn_iowrite32((_ah), (_reg), (_val)) macro
621 REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
623 REG_WRITE(_a, _r, \
626 REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
628 REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
H A Darn_phy.h529 REG_WRITE(ah, INI_RA((iniarray), r, 0), (regData)[r]); \
H A Darn_hw.h985 REG_WRITE(ah, INI_RA((iniarray), (r), 0), \