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Searched refs:REG_SPI4_DBG_STATUS (Results 1 – 2 of 2) sorted by relevance

/titanic_50/usr/src/uts/common/io/chxge/com/
H A Dvsc7321_reg.h145 #define REG_SPI4_DBG_STATUS CRA(0x5,0x0,0x32) /* Sampled ingress status */ macro
H A Dvsc7326_reg.h151 #define REG_SPI4_DBG_STATUS CRA(0x5,0x0,0x32) /* Sampled ingress status */ macro