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Searched refs:REG_RD (Results 1 – 21 of 21) sorted by relevance

/titanic_50/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/
H A Dhw_debug.h97 val = REG_RD(pdev, MISC_REG_CHIP_NUM); \
98 chip_rev = REG_RD(pdev, MISC_REG_CHIP_REV); \
99 chip_metal = REG_RD(pdev, MISC_REG_CHIP_METAL); \
119 val = REG_RD(pdev, offset); \
131 val = REG_RD(pdev, offset + i*(inc)); \
143 val1 = REG_RD(pdev, offset1); \
144 val2 = REG_RD(pdev, offset2); \
155 val1 = REG_RD(pdev, (offset1 + i*inc)); \
156 val2 = REG_RD(pdev, (offset2 + i*(inc))); \
169 val = REG_RD(pdev, offset);\
[all …]
H A Dlm_er.c91 val = REG_RD(pdev, MISC_REG_AEU_GENERAL_MASK); in lm_er_disable_close_the_gate()
112 val = REG_RD(pdev, IGU_REG_BLOCK_CONFIGURATION); in lm_er_set_234_gates()
224 sr_cnt = REG_RD(pdev, PXP2_REG_RD_SR_CNT); in lm_er_empty_tetris_buffer()
225 blk_cnt = REG_RD(pdev, PXP2_REG_RD_BLK_CNT); in lm_er_empty_tetris_buffer()
226 port_is_idle_0 = REG_RD(pdev, PXP2_REG_RD_PORT_IS_IDLE_0); in lm_er_empty_tetris_buffer()
227 port_is_idle_1 = REG_RD(pdev, PXP2_REG_RD_PORT_IS_IDLE_1); in lm_er_empty_tetris_buffer()
228 pgl_exp_rom2 = REG_RD(pdev, PXP2_REG_PGL_EXP_ROM2); in lm_er_empty_tetris_buffer()
229 pgl_b_reg_tags = REG_RD(pdev, PGLUE_B_REG_TAGS_63_32); in lm_er_empty_tetris_buffer()
269 pend_bits = REG_RD(pdev, IGU_REG_PENDING_BITS_STATUS); in lm_er_poll_igu_vq()
480 val = REG_RD(pdev, MISC_REG_AEU_ENABLE2_NIG_0); in lm_er_config_close_the_g8()
[all …]
H A Dlm_hw_access.c392 val = REG_RD(pdev,MISC_REG_SPIO_INT) ; in lm_setup_fan_failure_detection()
397 val = REG_RD(pdev,MISC_REG_SPIO_EVENT_EN) ; in lm_setup_fan_failure_detection()
432 swap_val = REG_RD(pdev, NIG_REG_PORT_SWAP); in lm_gpio_read()
433 swap_override = REG_RD(pdev, NIG_REG_STRAP_OVERRIDE); in lm_gpio_read()
491 reg_val = REG_RD(pdev, MISC_REG_GPIO); in lm_gpio_read()
537 swap_val = REG_RD(pdev, NIG_REG_PORT_SWAP); in lm_gpio_write()
538 swap_override = REG_RD(pdev, NIG_REG_STRAP_OVERRIDE); in lm_gpio_write()
557 gpio_reg = (REG_RD(pdev, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT); in lm_gpio_write()
616 gpio_reg = REG_RD(pdev, MISC_REG_GPIO); in lm_gpio_mult_write()
675 swap_val = REG_RD(pdev, NIG_REG_PORT_SWAP); in lm_gpio_int_write()
[all …]
H A Dlm_nvram.c72 val=REG_RD(pdev, MCP_REG_MCPR_NVM_SW_ARB); in acquire_nvram_lock()
123 val=REG_RD(pdev, MCP_REG_MCPR_NVM_SW_ARB); in release_nvram_lock()
170 val=REG_RD(pdev, MCP_REG_MCPR_NVM_COMMAND);
212 val=REG_RD(pdev, MCP_REG_MCPR_NVM_COMMAND);
237 val=REG_RD(pdev, MCP_REG_MCPR_NVM_ACCESS_ENABLE); in enable_nvram_access()
259 val=REG_RD(pdev, MCP_REG_MCPR_NVM_ACCESS_ENABLE); in disable_nvram_access()
311 val=REG_RD(pdev, MCP_REG_MCPR_NVM_COMMAND); in nvram_read_dword()
314 val=REG_RD(pdev, MCP_REG_MCPR_NVM_READ); in nvram_read_dword()
384 val=REG_RD(pdev, MCP_REG_MCPR_NVM_COMMAND); in nvram_write_dword()
H A Dlm_hw_init_reset.c414 tq_freed_cnt_last = tq_freed_cnt_start = REG_RD(PFDEV(pdev), pbf_reg_pN_tq_lines_freed_cnt); in lm_cleanup_after_flr()
415 tq_occ = tq_to_free = REG_RD(PFDEV(pdev), pbf_reg_pN_tq_occupancy); in lm_cleanup_after_flr()
423 tq_occ = REG_RD(PFDEV(pdev), pbf_reg_pN_tq_occupancy); in lm_cleanup_after_flr()
424 tq_freed_cnt_last = REG_RD(PFDEV(pdev), pbf_reg_pN_tq_lines_freed_cnt); in lm_cleanup_after_flr()
471 …inernal_freed_crd_last = inernal_freed_crd_start = REG_RD(PFDEV(pdev), pbf_reg_pN_internal_crd_fre… in lm_cleanup_after_flr()
472 credit_last = credit_start = REG_RD(PFDEV(pdev), pbf_reg_pN_credit); in lm_cleanup_after_flr()
473 init_crd = REG_RD(PFDEV(pdev), pbf_reg_pN_init_crd); in lm_cleanup_after_flr()
483 credit_last = REG_RD(PFDEV(pdev), pbf_reg_pN_credit); in lm_cleanup_after_flr()
484 inernal_freed_crd_last = REG_RD(PFDEV(pdev), pbf_reg_pN_internal_crd_freed); in lm_cleanup_after_flr()
534 tmp = REG_RD(pdev,CFC_REG_WEAK_ENABLE_PF); in lm_cleanup_after_flr()
[all …]
H A Dbnxe_hw_debug.c70 val = REG_RD(pdev, MISC_REG_CHIP_NUM); in lm_disable_timer()
77 val = REG_RD(pdev,TM_REG_EN_LINEAR0_TIMER); in lm_disable_timer()
87 val = REG_RD(pdev,TM_REG_LIN0_SCAN_ON); in lm_disable_timer()
97 val = REG_RD(pdev,TM_REG_EN_LINEAR1_TIMER); in lm_disable_timer()
107 val = REG_RD(pdev,TM_REG_LIN1_SCAN_ON); in lm_disable_timer()
128 val = REG_RD(pdev, MISC_REG_CHIP_NUM); in lm_enable_timer()
147 val = REG_RD(pdev,DORQ_REG_DQ_FILL_LVLF); in lm_get_doorbell_info()
151 val = REG_RD(pdev,DORQ_REG_DQ_FILL_LVL_MAX); in lm_get_doorbell_info()
155 val = REG_RD(pdev,DORQ_REG_DB_DIS_CNTR0); in lm_get_doorbell_info()
192 chip_num = REG_RD(pdev,MISC_REG_CHIP_NUM); in _vq_hoq()
[all …]
H A Dlm_hw_attn.c596 val = REG_RD(pdev, MISC_REG_GRC_TIMEOUT_ATTN); in lm_latch_attn_everest_processing()
801 nig_status_port = REG_RD(pdev, NIG_REG_STATUS_INTERRUPT_PORT0); in lm_nig_processing()
839 nig_status_port = REG_RD(pdev, NIG_REG_STATUS_INTERRUPT_PORT1); in lm_nig_processing()
900 mask_val=REG_RD(pdev, port_reg_name); in lm_handle_assertion_processing()
932 nig_mask = REG_RD(pdev, NIG_REG_MASK_INTERRUPT_PORT0 + 4*PORT_ID(pdev)); in lm_handle_assertion_processing()
994 val = REG_RD(pdev, IGU_REG_ATTENTION_ACK_BITS); in lm_handle_assertion_processing()
1011 val = REG_RD(pdev,CFC_REG_CFC_INT_STS); in lm_cfc_attn_everest_processing()
1023 valc = REG_RD(pdev,CFC_REG_CFC_INT_STS_CLR); in lm_cfc_attn_everest_processing()
1028 u32_t val = REG_RD(pdev,PXP_REG_PXP_INT_STS_0); in lm_pxp_attn_everest_processing()
1063 val = REG_RD(pdev, offset ); in lm_spio5_attn_everest_processing()
[all …]
H A Dlm_mcp.c145 shmem = REG_RD(pdev, MISC_REG_SHARED_MEM_ADDR); in lm_reset_mcp_prep()
171 shmem = REG_RD(pdev, MISC_REG_SHARED_MEM_ADDR); in lm_reset_mcp_comp()
191 val = REG_RD(pdev, shmem + validity_offset); in lm_reset_mcp_comp()
241 val = REG_RD(pdev, MISC_REG_DRIVER_CONTROL_15); in lm_reset_mcp()
285 val_rd = REG_RD(pdev, GRCBASE_MCP + 0x9c); in acquire_split_alr()
320 val= REG_RD(pdev, GRCBASE_MCP + 0x9c); in release_split_alr()
1106 reg = REG_RD(pdev, offset); in lm_mcp_check()
1110 if( REG_RD(pdev, offset) != reg ) in lm_mcp_check()
H A Dlm_power.c376 val = REG_RD(pdev, emac.emac_mode); in set_d0_power_state()
381 val = REG_RD(pdev, rpm.rpm_config); in set_d0_power_state()
449 pf0_pcie_status_control = REG_RD(pdev, pcicfg_device_control_offset); in lm_pcie_state_save_for_d3()
463 u32_t own_pcie_status_control = REG_RD(pdev, pcicfg_device_control_offset); in lm_pcie_state_restore_for_d0()
474 pf0_pcie_status_control = REG_RD(pdev, pcicfg_device_control_offset); in lm_pcie_state_restore_for_d0()
H A Dlm_sb.c104 intr_status = REG_RD(pdev, INTR_BLK_SIMD_ADDR_WOMASK(pdev)); in lm_get_interrupt_status_wo_mask()
120 intr_status = REG_RD(pdev, INTR_BLK_SIMD_ADDR_WMASK(pdev)); in lm_get_interrupt_status()
679 …REG_RD(pdev, (PORT_ID(pdev) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : MISC_REG_AEU_ENABLE1_FUNC_0_OUT_… in init_status_blocks()
681 …REG_RD(pdev, (PORT_ID(pdev) ? MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0 : MISC_REG_AEU_ENABLE2_FUNC_0_OUT_… in init_status_blocks()
683 …REG_RD(pdev, (PORT_ID(pdev) ? MISC_REG_AEU_ENABLE3_FUNC_1_OUT_0 : MISC_REG_AEU_ENABLE3_FUNC_0_OUT_… in init_status_blocks()
685 …REG_RD(pdev, (PORT_ID(pdev) ? MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0 : MISC_REG_AEU_ENABLE4_FUNC_0_OUT_… in init_status_blocks()
689 …REG_RD(pdev, (PORT_ID(pdev) ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 : MISC_REG_AEU_ENABLE5_FUNC_0_OUT_… in init_status_blocks()
984 while (!(REG_RD(pdev, igu_addr_ack) & sb_bit) && --cnt) in lm_int_igu_sb_cleanup()
989 if (!(REG_RD(pdev, igu_addr_ack) & sb_bit)) in lm_int_igu_sb_cleanup()
1005 while ((REG_RD(pdev, igu_addr_ack) & sb_bit) && --cnt) in lm_int_igu_sb_cleanup()
[all …]
H A Dlm_devinfo.c176 val = REG_RD(pdev, PCICFG_OFFSET + GRC_CONFIG_REG_PF_INIT_VF); in lm_get_sriov_info()
219 val = REG_RD(pdev, BAR_ME_REGISTER); in lm_get_function_num()
590 pdev->hw_info.grc_didvid = REG_RD(pdev, (PCICFG_OFFSET + PCICFG_VENDOR_ID_OFFSET)); in lm_get_bars_info()
612 tr_e = REG_RD(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ); in lm_get_bars_info()
613 tw_e = REG_RD(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_WRITE); in lm_get_bars_info()
614 m_e = REG_RD(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); in lm_get_bars_info()
632 val=REG_RD(PFDEV(pdev),MISC_REG_CHIP_NUM); in lm_get_chip_id_and_mode()
636 val=REG_RD(PFDEV(pdev),MISC_REG_CHIP_TYPE); in lm_get_chip_id_and_mode()
654 val=REG_RD(PFDEV(pdev),MISC_REG_CHIP_REV); in lm_get_chip_id_and_mode()
675 val=REG_RD(PFDEV(pdev),MISC_REG_CHIP_METAL); in lm_get_chip_id_and_mode()
[all …]
H A Dlm_phy.c77 return REG_RD(cb, reg_addr); in elink_cb_reg_read()
255 tmp=REG_RD(pdev,emac_base+EMAC_REG_EMAC_MDIO_MODE); in lm_mwrite()
274 tmp=REG_RD(pdev,emac_base+EMAC_REG_EMAC_MDIO_COMM); in lm_mwrite()
295 tmp=REG_RD(pdev,emac_base+EMAC_REG_EMAC_MDIO_MODE); in lm_mwrite()
329 val=REG_RD(pdev,emac_base+EMAC_REG_EMAC_MDIO_MODE); in lm_mread()
347 val=REG_RD(pdev,emac_base+EMAC_REG_EMAC_MDIO_COMM); in lm_mread()
372 val=REG_RD(pdev,emac_base+EMAC_REG_EMAC_MDIO_MODE); in lm_mread()
H A Dlm_dcbx.c2799 *buff = REG_RD(pdev, in lm_dcbx_read_remote_local_mib()
3134 *buff = REG_RD(pdev, in lm_dcbx_lldp_read_params()
3182 *buff = REG_RD(pdev, in lm_dcbx_lldp_read_params()
3401 *buff = REG_RD(pdev, in lm_dcbx_read_params()
3627 *buff = REG_RD(pdev, in lm_dcbx_read_params()
4151 *buff = REG_RD(pdev, in lm_dcbx_read_admin_mib()
4474 *buff = REG_RD(pdev, in lm_dcbx_init_lldp_updated_params()
H A Dlm_stats.c591 val = REG_RD(pdev, HC_REG_INT_MASK + 4*PORT_ID(pdev) ); in is_pending_stats_completion()
710 …dummy = REG_RD( pdev, emac_base + reg_start[i]+(j*sizeof(u32_t))) ; /*Clear stats registers by rea… in lm_stats_clear_emac_stats()
3712 pdev->vars.stats.stats_collect.stats_hw.misc_stats_query.tx_lpi_count = REG_RD(pdev, eee); in lm_stats_hw_collect()
/titanic_50/usr/src/uts/common/io/bnxe/577xx/common/
H A Dbnxe_clc.c67 #define REG_RD(cb, reg) elink_cb_reg_read(cb, reg) macro
69 #define EMAC_RD(cb, reg) REG_RD(cb, emac_base + reg)
162 REG_RD(cb, shmem2_base + \
347 u32 val = REG_RD(cb, reg); in elink_bits_en()
356 u32 val = REG_RD(cb, reg); in elink_bits_dis()
380 REG_RD(cb, params->lfa_base + in elink_check_lfa()
395 link_status = REG_RD(cb, params->shmem_base + in elink_check_lfa()
424 saved_val = REG_RD(cb, params->lfa_base + in elink_check_lfa()
433 saved_val = REG_RD(cb, params->lfa_base + in elink_check_lfa()
442 saved_val = REG_RD(cb, params->lfa_base + in elink_check_lfa()
[all …]
/titanic_50/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/fw/
H A Dbnxe_fw_funcs.c43 u32_t curr_cos = REG_RD(pdev, QM_REG_QVOQIDX_0 + q_num * 4); in ecore_map_q_cos()
70 reg_bit_map = REG_RD(pdev, reg_addr); in ecore_map_q_cos()
75 reg_bit_map = REG_RD(pdev, reg_addr); in ecore_map_q_cos()
82 reg_bit_map = REG_RD(pdev, reg_addr); in ecore_map_q_cos()
/titanic_50/usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/
H A Decore_init.h203 reg_val = REG_RD(pdev, mcp_attn_ctl_regs[i].addr); in ecore_set_mcp_parity()
268 reg_val = REG_RD(pdev, ecore_blocks_parity_data[i]. in ecore_clear_blocks_parity()
280 reg_val = REG_RD(pdev, MISC_REG_AEU_AFTER_INVERT_4_MCP); in ecore_clear_blocks_parity()
H A Decore_init_ops.h272 REG_RD(pdev, addr); in ecore_init_block()
540 val = REG_RD(pdev, write_arb_addr[i].l); in ecore_init_pxp_arb()
544 val = REG_RD(pdev, write_arb_addr[i].add); in ecore_init_pxp_arb()
548 val = REG_RD(pdev, write_arb_addr[i].ubound); in ecore_init_pxp_arb()
609 val = REG_RD(pdev, PCIE_REG_PCIER_TL_HDR_FC_ST); in ecore_init_pxp_arb()
/titanic_50/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/channel_vf/
H A Dlm_vf.c2947 val=REG_RD(PFDEV(pdev), IGU_REG_VF_CONFIGURATION); in lm_pf_enable_vf_igu_int()
2991 val = REG_RD(PFDEV(pdev), IGU_REG_VF_CONFIGURATION); in lm_pf_disable_vf_igu_int()
3341 tq_freed_cnt_last = tq_freed_cnt_start = REG_RD(PFDEV(pdev), pbf_reg_pN_tq_lines_freed_cnt); in lm_pf_cleanup_vf_after_flr()
3342 tq_occ = tq_to_free = REG_RD(PFDEV(pdev), pbf_reg_pN_tq_occupancy); in lm_pf_cleanup_vf_after_flr()
3348 tq_occ = REG_RD(PFDEV(pdev), pbf_reg_pN_tq_occupancy); in lm_pf_cleanup_vf_after_flr()
3349 tq_freed_cnt_last = REG_RD(PFDEV(pdev), pbf_reg_pN_tq_lines_freed_cnt); in lm_pf_cleanup_vf_after_flr()
3392 …inernal_freed_crd_last = inernal_freed_crd_start = REG_RD(PFDEV(pdev), pbf_reg_pN_internal_crd_fre… in lm_pf_cleanup_vf_after_flr()
3393 credit_last = credit_start = REG_RD(PFDEV(pdev), pbf_reg_pN_credit); in lm_pf_cleanup_vf_after_flr()
3394 init_crd = REG_RD(PFDEV(pdev), pbf_reg_pN_init_crd); in lm_pf_cleanup_vf_after_flr()
3402 credit_last = REG_RD(PFDEV(pdev), pbf_reg_pN_credit); in lm_pf_cleanup_vf_after_flr()
[all …]
/titanic_50/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/include/
H A Dlm5710.h518 …*(_unicore_intr_val_ptr) = REG_RD(_pdev, _nig_reg_name); …
4088 #define REG_RD(_pdev, _reg_offset) _reg_rd(_pdev, _reg_offset) macro
4101 #define REG_RD(_pdev, _reg_offset) \ macro
4140 #define REG_RD(_pdev, _reg_offset) _reg_rd(_pdev, _reg_offset) macro
4181 #define REG_RD(_pdev, _reg_offset) _reg_rd(_pdev, _reg_offset) macro
4230 … (REG_RD(_pdev, LM_SHMEM2_ADDR(_pdev, size)) > OFFSETOF(struct shmem2_region, field)))
4305 db_fill=REG_RD(pf_dev,DORQ_REG_DQ_FILL_LVLF); in DOORBELL()
4319 db_fill=REG_RD(pf_dev,DORQ_REG_DQ_FILL_LVLF); in DOORBELL()
/titanic_50/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/basic_vf/
H A Dlm_vf.c530 val=REG_RD(PFDEV(pdev), IGU_REG_VF_CONFIGURATION); in lm_vf_enable_igu_int()
574 val = REG_RD(PFDEV(pdev), IGU_REG_VF_CONFIGURATION); in lm_vf_disable_igu_int()