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Searched refs:REG_ADDR (Results 1 – 7 of 7) sorted by relevance

/titanic_50/usr/src/uts/sun4u/starcat/io/
H A Daxq.c50 #define REG_ADDR(b, o) (uint32_t *)((caddr_t)(b) + (o)) macro
425 softsp->axq_domain_ctrl = REG_ADDR(softsp->address, in axq_init()
427 softsp->axq_cdc_addrtest = REG_ADDR(softsp->address, in axq_init()
429 softsp->axq_cdc_ctrltest = REG_ADDR(softsp->address, in axq_init()
431 softsp->axq_cdc_datawrite0 = REG_ADDR(softsp->address, in axq_init()
433 softsp->axq_cdc_datawrite1 = REG_ADDR(softsp->address, in axq_init()
435 softsp->axq_cdc_datawrite2 = REG_ADDR(softsp->address, in axq_init()
437 softsp->axq_cdc_datawrite3 = REG_ADDR(softsp->address, in axq_init()
439 softsp->axq_cdc_counter = REG_ADDR(softsp->address, in axq_init()
441 softsp->axq_cdc_readdata0 = REG_ADDR(softsp->address, in axq_init()
[all …]
/titanic_50/usr/src/uts/sun4u/io/
H A Diocache.c86 #define REG_ADDR(b, o) (uint64_t *)((caddr_t)(b) + (o)) in stream_buf_init() macro
88 softsp->str_buf_ctrl_reg = REG_ADDR(address, OFF_STR_BUF_CTRL_REG); in stream_buf_init()
89 softsp->str_buf_flush_reg = REG_ADDR(address, OFF_STR_BUF_FLUSH_REG); in stream_buf_init()
90 softsp->str_buf_sync_reg = REG_ADDR(address, OFF_STR_BUF_SYNC_REG); in stream_buf_init()
91 softsp->str_buf_pg_tag_diag = REG_ADDR(address, STR_BUF_PAGE_TAG_DIAG); in stream_buf_init()
93 #undef REG_ADDR in stream_buf_init()
H A Dsysioerr.c142 #define REG_ADDR(b, o) (uint64_t *)((caddr_t)(b) + (o)) in sysio_err_init() macro
144 softsp->sysio_ecc_reg = REG_ADDR(address, OFF_SYSIO_ECC_REGS); in sysio_err_init()
145 softsp->sysio_ue_reg = REG_ADDR(address, OFF_SYSIO_UE_REGS); in sysio_err_init()
146 softsp->sysio_ce_reg = REG_ADDR(address, OFF_SYSIO_CE_REGS); in sysio_err_init()
147 softsp->sbus_err_reg = REG_ADDR(address, OFF_SBUS_ERR_REGS); in sysio_err_init()
149 #undef REG_ADDR in sysio_err_init()
H A Dsysiosbus.c725 #define REG_ADDR(b, o) (uint64_t *)((caddr_t)(b) + (o)) in sbus_init() macro
727 softsp->sysio_ctrl_reg = REG_ADDR(address, OFF_SYSIO_CTRL_REG); in sbus_init()
728 softsp->sbus_ctrl_reg = REG_ADDR(address, OFF_SBUS_CTRL_REG); in sbus_init()
729 softsp->sbus_slot_config_reg = REG_ADDR(address, OFF_SBUS_SLOT_CONFIG); in sbus_init()
730 softsp->intr_mapping_reg = REG_ADDR(address, OFF_INTR_MAPPING_REG); in sbus_init()
731 softsp->clr_intr_reg = REG_ADDR(address, OFF_CLR_INTR_REG); in sbus_init()
732 softsp->intr_retry_reg = REG_ADDR(address, OFF_INTR_RETRY_REG); in sbus_init()
733 softsp->sbus_intr_state = REG_ADDR(address, OFF_SBUS_INTR_STATE_REG); in sbus_init()
734 softsp->sbus_pcr = REG_ADDR(address, OFF_SBUS_PCR); in sbus_init()
735 softsp->sbus_pic = REG_ADDR(address, OFF_SBUS_PIC); in sbus_init()
[all …]
H A Diommu.c136 #define REG_ADDR(b, o) (uint64_t *)((caddr_t)(b) + (o)) in iommu_init() macro
138 softsp->iommu_ctrl_reg = REG_ADDR(address, OFF_IOMMU_CTRL_REG); in iommu_init()
139 softsp->tsb_base_addr = REG_ADDR(address, OFF_TSB_BASE_ADDR); in iommu_init()
140 softsp->iommu_flush_reg = REG_ADDR(address, OFF_IOMMU_FLUSH_REG); in iommu_init()
141 softsp->iommu_tlb_tag = REG_ADDR(address, OFF_IOMMU_TLB_TAG); in iommu_init()
142 softsp->iommu_tlb_data = REG_ADDR(address, OFF_IOMMU_TLB_DATA); in iommu_init()
144 #undef REG_ADDR in iommu_init()
/titanic_50/usr/src/uts/common/io/chxge/com/
H A Dmy3126.c69 #define OFFSET(REG_ADDR) (REG_ADDR << 2) argument
H A Dpm3393.c46 #define OFFSET(REG_ADDR) (REG_ADDR << 2) argument