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Searched refs:RD16_IO_REG (Results 1 – 7 of 7) sorted by relevance

/titanic_50/usr/src/uts/common/io/fibre-channel/fca/qlc/
H A Dql_isr.c192 while (RD16_IO_REG(ha, istatus) & RISC_INT) { in ql_isr_aif()
206 mbx = RD16_IO_REG(ha, mailbox_out[23]); in ql_isr_aif()
273 mbx = RD16_IO_REG(ha, semaphore); in ql_isr_aif()
279 mbx = RD16_IO_REG(ha, mailbox_out[0]); in ql_isr_aif()
295 ha->isp_rsp_index = RD16_IO_REG(ha, in ql_isr_aif()
508 mbx = RD16_IO_REG(ha, hccr); /* PCI posting */ in ql_isr_aif()
568 hccr_reg = RD16_IO_REG(ha, hccr); in ql_handle_uncommon_risc_intr()
693 ha->mcp->mb[cnt] = RD16_IO_REG(ha, in ql_mbx_completion()
758 handle = SHORT_TO_LONG(RD16_IO_REG(ha, mailbox_out[1]), in ql_async_event()
759 RD16_IO_REG(ha, mailbox_out[2])); in ql_async_event()
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H A Dql_init.c291 if ((RD16_IO_REG(ha, hccr) & HC_RISC_PAUSE) != in ql_pci_sbus_config()
303 if (RD16_IO_REG(ha, fb_cmd) == 6) { in ql_pci_sbus_config()
313 if ((RD16_IO_REG(ha, hccr) & HC_RISC_PAUSE) == in ql_pci_sbus_config()
325 if ((RD16_IO_REG(ha, ctrl_status) & ISP_FUNC_NUM_MASK) in ql_pci_sbus_config()
851 reg_data = RD16_IO_REG(ha, nvram); in ql_nvram_request()
1274 if ((RD16_IO_REG(ha, nvram) & 0x8000) == 0) { in ql_lock_nvram()
1277 if (RD16_IO_REG(ha, host_to_host_sema) & 1) { in ql_lock_nvram()
1283 if ((RD16_IO_REG(ha, host_to_host_sema) & 1) == 0) { in ql_lock_nvram()
2209 RD16_IO_REG(ha, mailbox_out[7]) == 4) { in ql_chip_diag()
2220 mr.mb[1] = RD16_IO_REG(ha, mailbox_out[1]); in ql_chip_diag()
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H A Dql_iocb.c114 cnt = RD16_IO_REG(ha, req_out); in ql_start_iocb()
286 cnt = RD16_IO_REG(ha, req_out); in ql_req_pkt()
1314 index = RD16_IO_REG(ha, mailbox_out[8]); in ql_isp_rcvbuf()
1316 index1 = RD16_IO_REG(ha, mailbox_out[8]); in ql_isp_rcvbuf()
H A Dql_ioctl.c463 data = RD16_IO_REG(ha, nvram); in ql_get_feature_bits()
811 word = RD16_IO_REG(ha, nvram); in ql_load_nvram()
840 word = RD16_IO_REG(ha, nvram); in ql_load_nvram()
H A Dql_api.c4290 RD16_IO_REG(ha, hccr), in ql_port_manage()
4291 RD16_IO_REG(ha, istatus)); in ql_port_manage()
11056 data = (uint16_t)(RD16_IO_REG(ha, ctrl_status) | in ql_flash_enable()
11100 data = (uint16_t)(RD16_IO_REG(ha, ctrl_status) & in ql_flash_disable()
11137 bank_select = (uint16_t)RD16_IO_REG(ha, ctrl_status); in ql_write_flash_byte()
11200 bank_select = RD16_IO_REG(ha, ctrl_status); in ql_read_flash_byte()
11222 data = (uint8_t)RD16_IO_REG(ha, flash_data); in ql_read_flash_byte()
13179 while ((RD16_IO_REG(ha, hccr) & HC_RISC_PAUSE) == 0) { in ql_2200_binary_fw_dump()
13274 while (RD16_IO_REG(ha, mailbox_out[0]) == MBS_BUSY) { in ql_2200_binary_fw_dump()
13291 while ((RD16_IO_REG(ha, hccr) & HC_RISC_PAUSE) == 0) { in ql_2200_binary_fw_dump()
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H A Dql_xioctl.c6038 (~(RD16_IO_REG(ha, gpiod))); in ql_blink_led()
6070 gpio_enable = (uint16_t)RD16_IO_REG(ha, gpioe); in ql_drive_led()
6075 gpio_data = (uint16_t)RD16_IO_REG(ha, gpiod); in ql_drive_led()
/titanic_50/usr/src/uts/common/sys/fibre-channel/fca/qlc/
H A Dql_api.h227 #define RD16_IO_REG(ha, regname) \ macro
1905 RD16_IO_REG(ha, istatus) & RISC_INT)