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Searched refs:Q_CSR (Results 1 – 2 of 2) sorted by relevance

/titanic_50/usr/src/uts/common/io/yge/
H A Dyge.c2078 CSR_WRITE_4(dev, Q_ADDR(port->p_rxq, Q_CSR), BMU_CLR_IRQ_PAR); in yge_handle_hwerr()
2083 CSR_WRITE_4(dev, Q_ADDR(port->p_txq, Q_CSR), BMU_CLR_IRQ_TCP); in yge_handle_hwerr()
2561 CSR_WRITE_4(dev, Q_ADDR(txq, Q_CSR), BMU_CLR_RESET); in yge_start_port()
2562 CSR_WRITE_4(dev, Q_ADDR(txq, Q_CSR), BMU_OPER_INIT); in yge_start_port()
2563 CSR_WRITE_4(dev, Q_ADDR(txq, Q_CSR), BMU_FIFO_OP_ON); in yge_start_port()
2584 CSR_WRITE_4(dev, Q_ADDR(rxq, Q_CSR), BMU_CLR_RESET); in yge_start_port()
2585 CSR_WRITE_4(dev, Q_ADDR(rxq, Q_CSR), BMU_OPER_INIT); in yge_start_port()
2586 CSR_WRITE_4(dev, Q_ADDR(rxq, Q_CSR), BMU_FIFO_OP_ON); in yge_start_port()
2601 CSR_WRITE_4(dev, Q_ADDR(rxq, Q_CSR), in yge_start_port()
2745 CSR_WRITE_4(dev, Q_ADDR(txq, Q_CSR), BMU_STOP); in yge_stop_port()
[all …]
H A Dyge.h386 #define Q_CSR 0x34 /* 32 bit BMU Control/Status Register */ macro