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Searched refs:PX_INTR_STATE_ENABLE (Results 1 – 5 of 5) sorted by relevance

/titanic_50/usr/src/uts/sun4/io/px/
H A Dpx_pec.c176 PX_ERR_LOW_PIL, PX_INTR_STATE_ENABLE, MSG_REC, in px_pec_msg_add_intr()
200 PX_ERR_PIL, PX_INTR_STATE_ENABLE, MSG_REC, in px_pec_msg_add_intr()
223 PX_INTR_STATE_ENABLE, MSG_REC, PCIE_FATAL_MSG)) != DDI_SUCCESS) { in px_pec_msg_add_intr()
H A Dpx_ib.h80 #define PX_INTR_STATE_ENABLE 1 /* enabled */ macro
H A Dpx_intr.c520 hdlp->ih_vector, hdlp->ih_pri, PX_INTR_STATE_ENABLE, 0, 0); in px_intx_ops()
679 PX_INTR_STATE_ENABLE, msiq_rec_type, msi_num); in px_msix_ops()
871 if (ih_p->ih_intr_state == PX_INTR_STATE_ENABLE) { in px_ks_update()
H A Dpx.c662 PX_INTR_STATE_ENABLE, MSG_REC, PCIE_PME_ACK_MSG) != DDI_SUCCESS) { in px_pwr_setup()
H A Dpx_ib.c1017 PX_INTR_STATE_ENABLE, msiq_rec_type, msi_num)) != DDI_SUCCESS) { in px_ib_set_msix_target()