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Searched refs:PS_T (Results 1 – 6 of 6) sorted by relevance

/titanic_50/usr/src/uts/intel/ia32/sys/
H A Dpsw.h72 #define PS_T 0x0100 /* trace enable bit */ macro
94 #define PSL_USERMASK (PS_ICC|PS_D|PS_T|PS_V|PS_P|PS_ACHK|PS_NT)
/titanic_50/usr/src/uts/intel/ia32/syscall/
H A Dgetcontext.c95 if ((rp->r_ps & PS_T) || (lwp->lwp_pcb.pcb_flags & REQUEST_STEP)) { in savecontext()
100 rp->r_ps &= ~PS_T; in savecontext()
156 if (lwptoregs(lwp)->r_ps & PS_T) in restorecontext()
292 if ((rp->r_ps & PS_T) || (lwp->lwp_pcb.pcb_flags & REQUEST_STEP)) { in savecontext32()
297 rp->r_ps &= ~PS_T; in savecontext32()
/titanic_50/usr/src/uts/intel/ia32/os/
H A Dsyscall.c465 if (rp->r_ps & PS_T) { in post_syscall()
467 rp->r_ps &= ~PS_T; in post_syscall()
692 rp->r_ps |= PS_T; in post_syscall()
696 rp->r_ps &= ~PS_T; in post_syscall()
/titanic_50/usr/src/uts/i86pc/os/
H A Dtrap.c1123 rp->r_ps &= ~PS_T; /* turn off trace */ in trap()
1326 rp->r_ps &= ~PS_T; in trap()
1508 rp->r_ps |= PS_T; in trap()
1512 rp->r_ps &= ~PS_T; in trap()
H A Dmp_startup.c202 wrmsr(MSR_AMD_SFMASK, (uint64_t)(uintptr_t)(PS_IE | PS_T)); in init_cpu_syscall()
/titanic_50/usr/src/uts/intel/ia32/ml/
H A Dexception.s943 andl $_BITNOT(PS_NT|PS_T|PS_IE), %ecx