Home
last modified time | relevance | path

Searched refs:PORT_REG (Results 1 – 4 of 4) sorted by relevance

/titanic_50/usr/src/uts/common/io/cxgbe/common/
H A Dt4_hw.c2148 u32 v = t4_read_reg(adap, PORT_REG(port, A_XGMAC_PORT_INT_CAUSE)); in xgmac_intr_handler()
2158 t4_write_reg(adap, PORT_REG(port, A_XGMAC_PORT_INT_CAUSE), v); in xgmac_intr_handler()
3464 t4_read_reg64(adap, PORT_REG(idx, A_MPS_PORT_STAT_##name##_L)) in t4_get_port_stats()
3547 t4_write_reg(adap, PORT_REG(idx, i), 0); in t4_clr_port_stats()
3550 t4_write_reg(adap, PORT_REG(idx, i), 0); in t4_clr_port_stats()
3574 t4_read_reg64(adap, PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L)) in t4_get_lb_stats()
3591 p->drop = t4_read_reg(adap, PORT_REG(idx, in t4_get_lb_stats()
3619 t4_write_reg(adap, PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_LO), in t4_wol_magic_enable()
3622 t4_write_reg(adap, PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_HI), in t4_wol_magic_enable()
3625 t4_set_reg_field(adap, PORT_REG(port, A_XGMAC_PORT_CFG2), F_MAGICEN, in t4_wol_magic_enable()
[all …]
H A Dt4_regs.h76 #define PORT_REG(idx, reg) (PORT_BASE(idx) + (reg)) macro
/titanic_50/usr/src/uts/common/io/cxgbe/t4nex/
H A Dt4_mac.c104 t4_read_reg64(sc, PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_##name##_L)) in t4_mc_getstat()
H A Dt4_sge.c3203 PORT_REG(pi->port_id, A_MPS_PORT_STAT_##name##_L)) in update_port_info_kstats()