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Searched refs:PIPE_START_VBLANK_INTERRUPT_STATUS (Results 1 – 2 of 2) sorted by relevance

/titanic_50/usr/src/uts/intel/io/drm/
H A Di915_irq.c529 else if (pipea_stats & (PIPE_START_VBLANK_INTERRUPT_STATUS| in i915_driver_irq_handler()
546 else if (pipeb_stats & (PIPE_START_VBLANK_INTERRUPT_STATUS| in i915_driver_irq_handler()
H A Di915_drv.h1285 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ macro