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Searched refs:PIPE_START_VBLANK_INTERRUPT_ENABLE (Results 1 – 2 of 2) sorted by relevance

/titanic_50/usr/src/uts/intel/io/drm/
H A Di915_irq.c527 pipea_stats &= ~(PIPE_START_VBLANK_INTERRUPT_ENABLE | in i915_driver_irq_handler()
544 pipeb_stats &= ~(PIPE_START_VBLANK_INTERRUPT_ENABLE | in i915_driver_irq_handler()
806 PIPE_START_VBLANK_INTERRUPT_ENABLE); in i915_enable_vblank()
825 PIPE_START_VBLANK_INTERRUPT_ENABLE); in i915_disable_vblank()
H A Di915_drv.h1273 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ macro