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Searched refs:PEC_CORE_AND_BLOCK_INTERRUPT_ENABLE (Results 1 – 2 of 2) sorted by relevance

/titanic_50/usr/src/uts/sun4u/io/px/
H A Dpx_hlib.c55 {PEC_CORE_AND_BLOCK_INTERRUPT_ENABLE, PX_CHIP_UNIDENTIFIED},
1613 CSR_XS(csr_base, PEC_CORE_AND_BLOCK_INTERRUPT_ENABLE, val); in hvio_pec_init()
1616 CSR_XR(csr_base, PEC_CORE_AND_BLOCK_INTERRUPT_ENABLE)); in hvio_pec_init()
H A Dpx_regs.h1398 #define PEC_CORE_AND_BLOCK_INTERRUPT_ENABLE 0x51800 macro