Searched refs:PCI_CONF_BASE3 (Results 1 – 17 of 17) sorted by relevance
| /titanic_50/usr/src/uts/sun4u/sys/pci/ |
| H A D | db21554_config.h | 52 #define DB_PCONF_DS_MEM2 PCI_CONF_BASE3
57 #define DB_PCONF_US_MEM1 DB_PCONF_SEC_HDR_OFF+PCI_CONF_BASE3
63 #define DB_SCONF_US_MEM1 PCI_CONF_BASE3
66 #define DB_SCONF_DS_MEM2 DB_SCONF_PRI_HDR_OFF+PCI_CONF_BASE3
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| /titanic_50/usr/src/uts/common/io/igb/ |
| H A D | igb_debug.c | 108 msix_bar = pci_config_get32(handle, PCI_CONF_BASE3); in pci_dump()
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| /titanic_50/usr/src/uts/common/sys/ |
| H A D | pci.h | 56 #define PCI_CONF_BASE3 0x1c /* base register 3, 4 bytes */ macro
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| /titanic_50/usr/src/uts/common/os/ |
| H A D | sunpci.c | 522 chsp->chs_base3 = pci_config_get32(confhdl, PCI_CONF_BASE3);
876 pci_config_put32(confhdl, PCI_CONF_BASE3, chs_p->chs_base3);
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| /titanic_50/usr/src/uts/common/io/e1000g/ |
| H A D | e1000g_debug.c | 421 pciconfig_bar(Adapter, PCI_CONF_BASE3, "PCI_CONF_BASE3"); in pciconfig_dump()
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| /titanic_50/usr/src/uts/common/io/ixgbe/ |
| H A D | ixgbe_debug.c | 233 msix_bar = pci_config_get32(handle, PCI_CONF_BASE3); in ixgbe_pci_dump()
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| /titanic_50/usr/src/uts/sun4/io/px/ |
| H A D | px_tools.c | 60 PCI_CONF_BASE3,
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| /titanic_50/usr/src/uts/sun4u/io/pci/ |
| H A D | pci_tools.c | 93 PCI_CONF_BASE3,
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| H A D | db21554.c | 1056 (off_t)(p_offset + PCI_CONF_BASE3))) & ~DB_IO_BIT)); in db_enable_io()
1068 (off_t)(s_offset + PCI_CONF_BASE3))) & ~DB_IO_BIT)); in db_enable_io()
1636 ph->bar3 = pci_config_get32(config_handle, hdr_off + PCI_CONF_BASE3); in db_pci_get_header()
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| /titanic_50/usr/src/uts/i86pc/io/pci/ |
| H A D | pci_tools.c | 71 PCI_CONF_BASE3,
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| /titanic_50/usr/src/cmd/pcitool/ |
| H A D | pcitool.c | 278 { PCI_CONF_BASE3, 4, "BAR3", "Base Address Register 3 (@1C)" },
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| /titanic_50/usr/src/uts/intel/io/hotplug/pcicfg/ |
| H A D | pcicfg.c | 163 PCI_CONF_BASE3, PCI_CONF_BASE2, PCI_CONF_BASE3,
435 pci_config_get32(config_handle, PCI_CONF_BASE3)); in pcicfg_dump_device_config()
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| /titanic_50/usr/src/uts/sun4/io/ |
| H A D | pcicfg.c | 203 PCI_CONF_BASE3, PCI_CONF_BASE2, PCI_CONF_BASE3,
464 pci_config_get32(config_handle, PCI_CONF_BASE3)); in pcicfg_dump_device_config()
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| /titanic_50/usr/src/uts/common/io/scsi/adapters/pmcs/ |
| H A D | pmcs_fwlog.c | 757 pci_config_get32(pwp->pci_acc_handle, PCI_CONF_BASE3)); in pmcs_dump_pcie_conf()
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| /titanic_50/usr/src/uts/common/io/fibre-channel/fca/qlge/ |
| H A D | qlge_dbg.c | 673 pci_config_get32(qlge->pci_handle, PCI_CONF_BASE3); in ql_dump_pci_config()
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| /titanic_50/usr/src/uts/common/io/cardbus/ |
| H A D | cardbus_cfg.c | 4366 pci_config_get32(config_handle, PCI_CONF_BASE3));
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| /titanic_50/usr/src/uts/common/io/fibre-channel/fca/qlc/ |
| H A D | ql_api.c | 15225 chs.chs_base3 = ql_pci_config_get32(ha, PCI_CONF_BASE3); in ql_save_config_regs()
15290 ql_pci_config_put32(ha, PCI_CONF_BASE3, chs_p->chs_base3); in ql_restore_config_regs()
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